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PCI9080 Datasheet(PDF) 53 Page - List of Unclassifed Manufacturers |
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PCI9080 Datasheet(HTML) 53 Page - List of Unclassifed Manufacturers |
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53 / 133 page  SECTION 4 PCI 9080 REGISTERS © ©PLX Technology, Inc., 1997 Page 45 Version 0.93 4.2.3 Runtime Registers Table 4-7. Runtime Registers PCI (Offset from Base Address) Local Access (Offset from Chip Select Address) To ensure software compatibility with other versions of the PCI 9080 family and to ensure compatibility with future enhancements, write a zero to all unused bits. 31 0 PCI/Local Writable EEPROM Writable 40h C0h Mailbox Register 0 1 Y Y 44h C4h Mailbox Register 1 1 Y Y 48h C8h Mailbox Register 2 Y N 4Ch CCh Mailbox Register 3 Y N 50h D0h Mailbox Register 4 Y N 54h D4h Mailbox Register 5 Y N 58h D8h Mailbox Register 6 Y N 5Ch DCh Mailbox Register 7 Y N 60h E0h PCI to Local Doorbell Register Y N 64h E4h Local to PCI Doorbell Register Y N 68h E8h Interrupt Control / Status Y N 6Ch ECh EEPROM Control, PCI Command Codes, User I/O Control, Init Control Y N 70h F0h Device ID Vendor ID N N 74h F4h Unused Revision ID N N 78h C0h Mailbox Register 0 1 Y N 7Ch C4h Mailbox Register 1 1 Y N Note: Mailbox registers 0 and 1 are always accessible at addresses 78h/C0h and 7Ch/C4. When the I2O feature is disabled (bit 0 of QSR register = 0), mailbox registers 0 and 1 are also accessible at PCI addresses 40h and 44h for PCI 9060 compatibility. When the I2O feature is enabled, the Inbound and Outbound Queue pointers are accessed at addresses 40 and 44, replacing the mailbox registers in the PCI address space. |
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