PCI9080 datasheet(90/133 Pages) ETC

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SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 82

Version 0.93

4.7.15 (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register

Table 4-89. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register

Field

Description

Read

Write

Value after Reset

Queue Decode Enable. When this bit is set, Mailbox registers 0 and 1 are replaced by

the Inbound and Outbound Queue Port Registers.

Yes

Queue Local Space Select. When this bit is set to 0, use local address space 0 bus

region descriptor for queue accesses. When this bit is set to 1, use local address

space 1 bus region descriptor for queue accesses.

Yes

Outbound Post List FIFO Prefetch Enable. When this bit is set, prefetching occurs

from the Outbound Post List FIFO if not empty.

Yes

Inbound Free List FIFO Prefetch Enable. When this bit is set, prefetching occurs from

the Inbound Free List FIFO if not empty.

Yes

Inbound Post List FIFO Interrupt Mask. Interrupt is masked when bit is set.

Yes

Inbound Post List FIFO Interrupt. This bit is set when the Inbound Post List FIFO

is not empty. This bit is not effected by the interrupt mask bit.

Yes

Outbound Free List FIFO Overflow Interrupt Mask. Interrupt is masked when bit is set.

Yes

Outbound Free List FIFO Overflow Interrupt. This bit is set when the Outbound Free

List FIFO becomes full. A local LSERR (NMI) interrupt is generated. Writing a 1 clears

the interrupt.

Yes

Yes/Clr

31:8

Unused.

Yes

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