PCI9080 datasheet(34/133 Pages) ETC

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SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 26

Version 0.93

3.6.3.2 PCI to Local Bus DMA Transfer

Local Bus Arbitration:

PCI Bus Arbitration:

• Releases control of the PCI bus

whenever the FIFO becomes full,

terminal count is reached, the PCI

latency timer expires and PCI GRANT

de-asserts, a PCI Disconnect is received,

or a Direct Local to PCI request is

pending.

Rearbitrates for control of the PCI bus

when the preprogrammed number of

empty entries in the FIFO becomes

available, or after two PCI clocks if a

disconnect was received.

•

PCI

Arbitration

Local Bus

Arbitration

FIFO

•

Load FIFO with

PCI Bus

Read Cycles

Unload FIFO with

Local Bus

Write Cycles

•

Local Interrupt Generation

(Programmable)

Done

Chaining: Terminal

Count for Current

Descriptor

•

PCI Interrupt Generation

(Programmable)

Done

Chaining: Terminal

Count for Current

Descriptor

GNT# REQ# LHOLDA LHOLD

Releases control of the local bus whenever

the FIFO becomes empty, the local latency

timer expires, the BREQ input is asserted, or

a Direct PCI to Local Bus request is pending.

Rearbitrates for control of the local bus

when the preprogrammed number of

entries becomes available in the FIFO or

the PCI terminal count is reached. If the

latency timer has expired, waits until the

pause timer expires.

• At the start of each block transfer, in

Chaining mode only, loads the DMA

Registers by reading four Lwords

from the address specified in the

Next Descriptor Pointer Register.

Chaining Mode Descriptors:

• At the start of each block transfer, in

Chaining mode only, loads the DMA

Registers by reading four Lwords

from the address specified in the

Next Descriptor Pointer Register.

Chaining Mode Descriptors:

Figure 3-10. PCI to Local Bus DMA Data Transfer Operation

3.6.3.3 Unaligned Transfers

For unaligned local to PCI transfers, the PCI 9080 reads

a partial Lword from the local bus. It then continues to

read Lwords from the local bus. The Lwords are

assembled, aligned to the PCI bus address and loaded

into the FIFO.

For PCI to local transfers, Lwords are read from the PCI

bus and loaded into the FIFO. On the local side, the

Lwords are assembled from the FIFO, aligned to the

local bus address and written to the local bus. On both

the local and PCI buses, the byte enables for writes

determine LA0 and LA1 for the start of a transfer. For

the last transfer, the byte enables specify the bytes to be

written. All reads are Lwords.

3.6.4 Demand Mode DMA

A bit in the DMA Configuration Registers specifies that

the channel operates in Demand Mode. In Demand

Mode, the user sets up the configuration registers of the

DMA controller and initiates a transfer. The DMA

controller transfers data when it asserts the DREQ[1:0]#

input of the DMA channel. The DMA controller then

asserts DACK[1:0]# to indicate that the current local bus

transfer is in response to the DREQ[1:0]# input. The

DMA controller continues to transfer data until it reaches

the transfer count or until DREQ[1:0]# is de-asserted.

The minimum transfer size per DREQ[1:0]# input is one

Lword (32 bits). This may result in multiple transfers for

an 8- or 16-bit bus. Refer to the timing diagrams in

Section 8, “Timing Diagrams.”

3.6.5 DMA Priority

DMA Channel 0 priority, DMA Channel 1 priority, or

rotating priority can be specified in the DMA Arbitration

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