PCI9080 datasheet(35/133 Pages) ETC

35 / 133 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 27

Version 0.93

3.6.6 DMA Arbitration

The PCI 9080 DMA controller releases control of the

local bus (de-asserts LHOLD) when one of the following

occurs:

•

Its FIFOs are full in a local to PCI transfer

•

Its FIFOs are empty in a PCI to local transfer

•

The Local Bus Latency Timer expires (if enabled)

•

The BREQ input is asserted (BREQ can be enabled

or disabled, or gated with a latency timer before the

PCI 9080 gives up the local bus)

•

A Direct Slave access is pending

•

EOT input is received (if enabled)

The DMA controller releases control of the PCI bus

when one of the following occurs:

•

The FIFOs are full or empty

•

When the PCI Latency Timer expires and it loses

the PCI grant signal

•

It receives a Target Disconnect response

It de-asserts its PCI bus request (REQ#) for a minimum

of two PCI clocks.

3.6.6.1 End of Transfer (EOT0# or EOT1#)

Input

When

asserted,

current

DMA

transfer

terminates,

regardless of the transfer size. Local transfers will

terminate after the current cycle. PCI transfer will

terminate immediately if transfer is from PCI to local. If

the transfer is from local to PCI, the PCI 9080 finishes

transferring all data in the internal FIFO and terminates

the DMA transfer

3.6.6.2 Local Latency and Pause Timers

A Local Bus Latency Timer and Local Bus Pause Timer

are programmable with the DMA Arbitration Register. If

the local latency timer expires, the PCI 9080 completes

the current Lword transfer and releases LHOLD. After its

programmable

Pause

Timer

expires,

reasserts

LHOLD. When it receives LHOLDA, it continues the

transfer. The

PCI bus transfer continues until the FIFO is empty for a

local to PCI transfer or until it is full for a PCI to local

transfer.

3.7 BREQ INPUT

When the PCI 9080 owns the local bus, both its LHOLD

output and LHOLDA input are asserted. When the PCI

9080 samples BREQ asserted during a DMA transfer or

a Direct Slave write transfer, it gives up the local bus

within two Lword transfers by de-asserting LHOLD and

floating its local bus outputs if BREQ is gated or

disabled, or if gating is enabled and the Local Bus

Latency Timer expires. The Local Arbiter can now grant

the local bus to another local master. After the PCI 9080

samples that its LHOLDA is de-asserted and its local

pause timer is zero, it re-asserts LHOLD to request the

local bus. When the PCI 9080 receives LHOLDA, it

drives the bus and continues from where it left off.

3.8 DOORBELL REGISTERS

There are two 32 bit doorbell interrupt/status registers in

the PCI 9080. One is assigned to the PCI bus interface

and while the other is assigned to the local bus

interface.

The local processor can generate a PCI bus interrupt by

writing any number other than all zeroes to the PCI to

local doorbell register.

A PCI host can generate a local bus interrupt by writing

any number other than all zeroes to the local to PCI

doorbell register.

3.9 MAILBOX REGISTERS

There are eight 32 bit mailbox registers in the PCI 9080

that can be written to and read from both buses. These

registers can be used to pass command and status

information directly between local and PCI bus devices.

A local interrupt can be generated, if enabled, when the

PCI host writes to one of the first four mailbox registers.

PCI9080 Datasheet(PDF) 35 Page - List of Unclassifed Manufacturers

PCI9080 Datasheet(HTML) 35 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL