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Data Sheet

AD5758

Rev. 0 | Page 35 of 72

the VIOUT pin in current mode to determine the user-

programmable value at which to set VDPC+.

DC-to-DC Converter Settling Time

When in DPC current mode, the settling time is dominated by the

settling time of the dc-to-dc converter and is typically 200 μs

without the digital slew rate control feature enabled. To reduce

initial VIOUT waveform overshoot without adding a capacitor on

VIOUT and thereby affecting HART operation, enable the digital

slew rate control feature using the DAC_CONFIG register (see

Table 33).

Table 11 shows the typical settling time for each of the dc-to-

dc converter modes. All values shown assume the use of the

components recommended by Analog Devices, Inc., listed in

Table 10. The achievable settling time in any given application is

dependent on the choice of external inductor and capacitor

components used, as well as the current-limit setting of the dc-

to-dc converter.

Table 11. Settling Time vs. DC-to-DC Converter Mode

DC-to-DC Converter Mode

Settling Time (μs)

DPC Current Mode

200

PPC Current Mode

DPC Voltage Mode

DC-to-DC Converter Inductor Selection

For typical 4 mA to 20 mA applications, a 47 μH inductor (per

Table 10), combined with the switching frequency of 500 kHz,

allows up to 24 mA to be driven into a load resistance of up to 1 kΩ

with an AVDD1 supply of greater than 24 V + headroom. It is

important to ensure that the peak current does not cause the

inductor to saturate, especially at the maximum ambient

temperature. If the inductor enters saturation mode, it results in

a decrease in efficiency. Larger size inductors translate to lower

core losses. The slew rate control feature of the AD5758 can be

used to limit peak currents during slewing. Program an appropriate

current limit (via the DCDC_CONFIG2 register) to shut off the

internal switch if the inductor current reaches that limit.

DC-to-DC Converter Input and Output Capacitor Selection

The output capacitor, CDCDC, affects the ripple voltage of the dc-

to-dc converter and limits the maximum slew rate at which the

output current can rise. The ripple voltage is directly related to

the output capacitance. The CDCDC capacitor recommended by

Analog Devices (see Table 10), combined with the recommended

47 μH inductor, results in a 500 kHz ripple with amplitude less

than 50 mV and guarantees stability and operation with HART

capability across all operating modes.

For high voltage capacitors, the size of the capacitor is often an

indication of the charge storage ability. It is important to

characterize the dc bias voltage vs. capacitance curve for this

capacitor. Any capacitance values specified are with reference to

a dc bias corresponding to the maximum VDPC+ voltage in the

application. As well as the voltage rating, the temperature range

of the capacitor must also be considered for a given application.

These considerations are key in selection of the components

described in Table 10.

The input capacitor, CIN, provides much of the dynamic current

required for the dc-to-dc converter, and a low effective series

resistance (ESR) component is recommended. For the AD5758,

a low ESR tantalum or ceramic capacitor of 4.7 μF (1206 size)

in parallel with a 0.1 μF (0402 size) capacitor is recommended.

Ceramic capacitors must be chosen carefully because they can

exhibit a large sensitivity to dc bias voltages and temperature.

X5R or X7R dielectrics are preferred because these capacitors

remain stable over wider operating voltage and temperature ranges.

Care must be taken if selecting a tantalum capacitor to ensure a

low ESR value.

CLKOUT

The AD5758 can provide a CLKOUT signal to the system for

synchronization purposes. This signal is programmable to eight

frequency options between 416 kHz and 588 kHz, with the

default option being 500 kHz—the same switching frequency of

the dc-to-dc converter. This feature is configured in the

GP_CONFIG1 register and is disabled by default

INTERDIE 3-WIRE INTERFACE

A 3-wire interface is used to communicate between the two die

in the AD5758. The 3-wire interface master is located on the

main die, and the 3-wire interface slave is on the dc-to-dc die.

The three interface signals are data, DCLK (running at

MCLK/8), and interrupt.

The main purpose of the 3-wire interface is to read from or write

to the DCDC_CONFIG1 and DCDC_CONFIG2 registers.

Addressing these registers via the SPI interface initiates an

internal 3-wire interface transfer from the main die to the dc-to-

dc die. The 3-wire interface master on the main die initiates

writes and reads to the registers on the dc-to-dc die using

DCLK as the serial clock. The slave uses an interrupt signal to

the dc-to-dc die to indicate that a read of the dc-to-dc die

internal status register is required.

For every 3-wire interface write, an automatic read and compare

process can be enabled (default case) to ensure that the contents

of the copy of the DCDC_CONFIGx registers on the main die

match the contents of the registers on the dc-to-dc die. This

comparison is performed to ensure the integrity of the digital

circuitry on the dc-to-dc die. With this feature enabled, a 3-wire

interface transfer takes approximately 300 μs. When disabled,

this transfer time reduces to 30 μs.

The BUSY_3WI flag in the DCDC_CONFIG2 register is asserted

during the 3-wire interface transaction. The BUSY_3WI flag

is also set when the user updates the DAC range (via the DAC_

CONFIG register, Bits[4:0]) due to the internal calibration memory

refresh caused by this action, which requires a 3-wire interface

transfer between the two die. A write to either of the DCDC_

CONFIGx registers must not be initiated while BUSY_3WI is

asserted. If a write occurs while BUSY_3WI is asserted, the new

write is delayed until the current 3-wire interface (3WI) transfer

completes.

AD5758 Datasheet(PDF) 35 Page - Analog Devices

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