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AD5758

Data Sheet

Rev. 0 | Page 16 of 72

Pin No.

Mnemonic

Description

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. In write mode, this pin

operates at clock speeds of up to 50 MHz (depending on the VLOGIC voltage). In read mode, the maximum SCLK

speed is 15 MHz (depending on the VLOGIC voltage). See Table 3 for the timing specifications.

SDI

Serial Data Input. Data must be valid on the falling edge of SCLK.

SYNC

Frame Synchronization Signal for the Serial Interface. Active low input. While SYNC is low, data is transferred in on

the falling edge of SCLK.

AD1

Address Decode 1 for the DUT on the Board.

AD0

Address Decode 0 for the DUT on the Board.

FAULT

Fault Pin. Active low, open-drain output. This pin is high impedance when no faults are detected and is asserted

low when certain faults are detected, for example, an open circuit in current mode, a short circuit in voltage mode,

a CRC error, or an overtemperature error (see the Output Fault section). This pin must be connected to VLOGIC with a 10 kΩ

pull-up resistor.

AVSS

Negative Analog Supply. The voltage range is from 0 V to −33 V. If using the device solely for unipolar current

output purposes, AVSS can be 0 V. For a unipolar voltage output, AVSS (maximum) is −2.5 V. When using bipolar

output ranges, VOUT/IOUT headroom must be obeyed when calculating the AVSS maximum, for example, for a ±10 V

output, the AVSS maximum is −12.5 V. See the AVSS Considerations section for an important note on power supply

sequencing.

−VSENSE

Sense Connection for the Negative Voltage Output Load Connection for VOUT Mode. This pin must stay within ±10 V

of AGND for specified operation. For specified operation, AVSS tracks −VSENSE with respect to AGND. If remote

sensing is not being used, short this pin to AGND.

CCOMP

Optional Compensation Capacitor Connection for the Voltage Output Buffer. Connecting a 220 pF capacitor

between this pin and the VIOUT pin allows the voltage output to drive up to 2 μF. The addition of this capacitor

reduces the bandwidth of the output amplifier, increasing the settling time.

+VSENSE

Sense Connection for the Positive Voltage Output Load Connection for Voltage Output Mode. If remote sensing is

not being used, short this pin to VIOUT via a series 1 kΩ resistor.

VIOUT

Voltage/Current Output Pin. VIOUT is a shared pin, providing either a buffered output voltage or current.

VIOUT_INT

Fault Protect Switch Internal Node. The inside of the fault protect switch is routed to this pin.

VDPC+

Positive Supply for Current and Voltage Output Stage. To use the dc-to-dc feature of the device, connect as shown

in Figure 77.

PGND1

Power Ground.

EPAD

Exposed Pad. Connect the exposed pad to the potential of the AVSS pin, or, alternatively, it can be left electrically

unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal

performance.

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