AD5758 datasheet(14/72 Pages) AD

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AD5758

Data Sheet

Rev. 0 | Page 14 of 72

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to

100 mA do not cause silicon controlled rectifier (SCR) latch-up.

Table 4.

Parameter

Rating

AVDD1 to AGND, DGND

−0.3 V to +44 V

AVSS to AGND, DGND

+0.3 V to −33 V

AVDD1 to AVSS

−0.3 V to +66 V

AVDD2, VDPC+ to AGND, DGND

−0.3 V to +35 V

AVDD2, VDPC+ to AVSS

−0.3 V to +55 V

VLOGIC to DGND

−0.3 V to +7 V

Digital Inputs to DGND (SCLK,

SDI, SYNC, AD0, AD1, RESET,

LDAC)

−0.3 V to VLOGIC + 0.3 V or +7 V

(whichever is less)

Digital Outputs to DGND (FAULT,

SDO, CLKOUT)

−0.3 V to VLOGIC + 0.3 V or +7 V

(whichever is less)

REFIN, REFOUT, VLDO, CHART to

AGND

−0.3 V to AVDD2 + 0.3 V or +7 V

(whichever is less)

RA to AGND

−0.3 V to +4.5 V

RB to AGND

−0.3 V to +4.5 V

VIOUT to AGND

±35 V

VIOUT_INT to AGND

±35 V

+VSENSE to AGND

±35 V

−VSENSE to AGND

±35 V

CCOMP to AGND

AVSS − 0.3 V to VDPC+ + 0.3 V

SW+ to AGND

−0.3 V to AVDD1 + 0.3 V or +33 V

(whichever is less)

AGND, DGND to REFGND

−0.3 V to +0.3 V

AGND, DGND to PGND1

−0.3 V to +0.3 V

Industrial Operating Temperature

Range (TA)1

−40°C to +115°C

Storage Temperature Range

−65°C to +150°C

Junction Temperature (TJ max)

125°C

Power Dissipation

(TJ maximum − TA)/θJA

Lead Temperature

JEDEC industry standard

Soldering

J-STD-020

1 Power dissipated on the chip must be derated to keep the junction

temperature below 125°C.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

Table 5. Thermal Resistance

Package Type

θJA

θJC

Unit

CP-32-301

°C/W

1 Test Condition 1: thermal impedance simulated values are based on a

JEDEC 2S2P thermal test board with thermal vias. See JEDEC JESD51.

ESD CAUTION

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