AD5758 datasheet(11/72 Pages) AD

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Data Sheet

AD5758

Rev. 0 | Page 11 of 72

TIMING CHARACTERISTICS

AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = −15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REGND =

PGND1 = 0 V; REFIN = 2.5 V external; voltage output: RL = 1 kΩ, CL = 220 pF; current output: RL = 300 Ω; all specifications at TA =

−40°C to +115°C, unless otherwise noted.

Table 3.

Parameter1, 2, 3

1.71 V ≤ VLOGIC < 3 V

3 V ≤ VLOGIC ≤ 5.5 V

Unit

Description

ns min

SCLK cycle time, write operation

120

ns min

SCLK cycle time, read operation

ns min

SCLK high time, write operation

ns min

SCLK high time, read operation

ns min

SCLK low time, write operation

ns min

SCLK low time, read operation

ns min

SYNC falling edge to SCLK falling edge setup time, write

operation

ns min

SYNC falling edge to SCLK falling edge setup time, read

operation

ns min

24th/32nd SCLK falling edge to SYNC rising edge

500

ns min

SYNC high time (all register writes outside of those listed

in this table)

1.5

μs min

SYNC high time (DAC_INPUT register write)

500

μs min

SYNC high time (DAC_CONFIG register write, where the

Range[3:0] bits change; see the Calibration Memory CRC

section)

ns min

Data setup time

ns min

Data hold time

750

ns min

LDAC falling edge to SYNC rising edge

t10

1.5

μs min

SYNC rising edge to LDAC falling edge

t11

250

ns min

LDAC pulse width low

t12

600

ns max

LDAC falling edge to DAC output response time, digital

slew rate control disabled.

μs max

LDAC falling edge to DAC output response time, digital

slew rate control enabled.

t13

See the AC Performance Characteristics section

μs max

DAC output settling time

t14

1.5

μs max

SYNC rising edge to DAC output response time (LDAC = 0)

t15

μs min

RESET pulse width

t16

ns max

SCLK rising edge to SDO valid

t17

100

μs min

RESET rising edge to 1st SCLK falling edge after SYNC

falling edge (t17 does not appear in the timing diagrams)

1 Guaranteed by design and characterization; not production tested.

2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VLOGIC) and timed from a voltage level of 1.2 V. tR is rise time. tF is fall time.

3 See Figure 2, Figure 3, Figure 4, and Figure 5.

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