AD5758 datasheet(15/72 Pages) AD

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Data Sheet

AD5758

Rev. 0 | Page 15 of 72

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

23 AD0

NOTES

1. NIC = NOT INTERNALLY CONNECTED.

2. CONNECT THE EXPOSED PAD TO THE POTENTIAL

OF THE AVSS PIN, OR, ALTERNATIVELY, IT CAN BE

LEFT ELECTRICALLY UNCONNECTED. IT IS

RECOMMENDED THAT THE PAD BE THERMALLY

CONNECTED TO A COPPER PLANE FOR ENHANCED

THERMAL PERFORMANCE.

22 AD1

FAULT

SYNC

SDI

SW+

NIC

AGND

REFGND

SCLK

CLKOUT

AD5758

TOP VIEW

(Not to Scale)

AVDD1

AVDD2

LDAC

Figure 6. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

SW+

Switching Output for the DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 77.

AVDD1

Positive Analog Supply. The voltage range is from 7 V to 33 V.

AVDD2

Positive Low Voltage Analog Supply. The voltage range is from 5 V to 33 V.

NIC

Not Internally Connected. This pin is not internally connected.

AGND

Ground Reference Point for the Analog Circuitry. This pin must be connected to 0 V.

REFGND

Ground Reference Point for Internal Reference. This pin must be connected to 0 V.

External Current Setting Resistor. An external, precision, low drift 13.7 kΩ current setting resistor can be connected

between RA and RB to improve the current output temperature drift performance. It is recommended that the

external resistor be placed as close as possible to the AD5758.

External Current Setting Resistor. An external, precision, low drift 13.7 kΩ current setting resistor can be connected

between RA and RB to improve the current output temperature drift performance. It is recommended that the

external resistor be placed as close as possible to the AD5758.

REFIN

External 2.5 V Reference Voltage Input.

REFOUT

Internal 2.5 V Reference Voltage Output. REFOUT must be connected to REFIN to use the internal reference. A

capacitor between REFOUT and REFGND is not recommended.

CHART

HART Input Connection. The HART signal must be ac-coupled to this pin. If HART is not being used, leave this pin

unconnected. This pin is disconnected from the HART summing node by default and can be connected via the

HART_EN bit in the GP_CONFIG1 register.

VLDO

3.3 V LDO Output Voltage. VLDO must be decoupled to AGND with a 0.1 μF capacitor.

VLOGIC

Digital Supply. The voltage range is from 1.71 V to 5.5 V. VLOGIC must be decoupled to DGND with a 0.1 μF capacitor.

SDO

Serial Data Output. This pin clocks data from the serial register in readback mode. The maximum SCLK speed for

readback mode is 15 MHz (depending on the VLOGIC voltage). See Table 3.

DGND

Digital Ground.

RESET

Hardware Reset. Active low input. Do not write an SPI command within 100 μs of issuing a reset (using the

hardware RESET pin or via software).

LDAC

Load DAC. Active low input. This pin updates the DAC_OUTPUT register and, consequently, the DAC output. Do not

assert LDAC within the window of 500 ns before the rising edge of SYNC or 1.5 μs after the rising edge of SYNC (see

Table 3 for the timing specifications).

CLKOUT

Optional Clock Output Signal (Disabled by Default). This pin is a divided down version of the internal 10 MHz

oscillator (MCLK) and is configured in the GP_CONFIG1 register.

AD5758 Datasheet(PDF) 15 Page - Analog Devices

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