AD5758 datasheet(38/72 Pages) AD

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AD5758

Data Sheet

Rev. 0 | Page 38 of 72

The following equation describes the slew rate as a function of

the step size, the update clock frequency, and the LSB size:

Size

LSB

Frequency

Clock

Update

Size

Step

Change

Output

Time

Slew





where:

Slew Time

is expressed in seconds.

Output Change

is expressed in amps for current output mode or

volts for voltage output mode.

When the slew rate control feature is enabled, all output changes

occur at the programmed slew rate. For example, if the WDT times

out and an automatic clear occurs, the output slews to the clear

value at the programmed slew rate (setting the CLEAR_NOW_

EN bit in the GP_CONFIG1 register overrides this default behavior

to cause the output to update to the clear code immediately,

rather than at the programmed slew rate).

The update clock frequency for any given value is the same for

all output ranges. The step size, however, varies across output

ranges for a given value of step size because the LSB size is

different for each output range.

DEVICE UNDER TEST (DUT) ADDRESS PINS

The DUT address pins (AD0 and AD1) are used in conjunction

with the DUT address bits within the SPI frame (see Table 12)

to determine which AD5758 device is being addressed by the

system controller. With the two address pins, up to four devices

can be independently addressed on one board.

SPI Interface and Diagnostics

The AD5758 is controlled over a 4-wire serial interface with an

8-bit cyclic redundancy check (CRC-8) enabled by default. The

input shift register is 32 bits wide, and data is loaded into the

device MSB first under the control of a serial clock input, SCLK.

Data is clocked in on the falling edge of SCLK. If CRC is disabled,

the serial interface is reduced to 24 bits; a 32-bit frame is still

accepted but the last 8 bits are ignored.

Table 12. Writing to a Register (CRC enabled)

MSB

LSB

D31

[D30:D29]

[D28:D24]

[D23:D8]

[D7:D0]

Slip bit

DUT address

Data

CRC

As shown in Table 12, every SPI frame contains two DUT

address bits. These bits must match the hardware DUT address

pins (AD0 and AD1) for a particular device to accept the SPI

frame on the bus.

SPI Cyclic Redundancy Check

To verify that data has been received correctly in noisy environ-

ments, the AD5758 offers the option of CRC based on a CRC-8.

The device controlling the AD5758 generates an 8-bit frame

check sequence using the following polynomial:

(x) = x8 + x2 + x1 + 1

This sequence is added to the end of the data-word, and 32 bits

are sent to the AD5758 before taking SYNC high.

If the SPI_CRC_EN bit is set high (default state), the user must

supply a frame of exactly 32 bits wide that contains the 24 data bits

and 8-bit CRC. If the CRC check is valid, the data is written to

the selected register. If the CRC check fails, the data is ignored, the

FAULT pin goes low and the FAULT pin status bit and the digital

diagnostic status bit (DIG_DIAG_STATUS) in the status register

are asserted. A subsequent readback of the DIGITAL_DIAG_

RESULTS register reveals that the SPI_CRC_ERR bit is also set.

This register is a per bit, write to clear register (see the Sticky

Diagnostic Results Bits section); therefore, the SPI_CRC_ERR bit

can be cleared by writing a 1 to Bit D0 of the DIGITAL_DIAG_

RESULTS register. Doing so clears the SPI_CRC_ERROR bit

and causes the FAULT pin to return high (assuming that there are

no other active faults). When configuring the FAULT_PIN_

CONFIG register, the user can decide whether the SPI CRC

error affects the FAULT pin. See the FAULT Pin Configuration

used for both the transmission and receipt of data packets.

SDI

SYNC

SCLK

UPDATE ON SYNC HIGH

MSB

D23

LSB

24-BIT DATA

24-BIT DATA TRANSFER—NO CRC ERROR CHECKING

SDI

FAULT

SYNC

SCLK

UPDATE ON SYNC HIGH

ONLY IF CRC CHECK PASSED

FAULT PIN GOES LOW

IF CRC CHECK FAILS

MSB

D31

LSB

24-BIT DATA

8-BIT CRC

32-BIT DATA TRANSFER WITH CRC ERROR CHECKING

Figure 81. CRC Timing (Assume LDAC = 0)

SPI Interface Slip Bit

A further enhancement to the robustness of the interface is the

addition of the slip bit. The MSB of the SPI frame must equal

the inverse of the MSB − 1 for the frame to be considered valid.

If an incorrect slip bit is detected, the data is ignored and the

SLIPBIT_ERROR bit in the DIGITAL_DIAG_RESULTS register

is asserted.

AD5758 Datasheet(PDF) 38 Page - Analog Devices

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