AD5758 datasheet(39/72 Pages) AD

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Data Sheet

AD5758

Rev. 0 | Page 39 of 72

SPI Interface SCLK Count Feature

An SCLK count feature is also built into the SPI diagnostics,

meaning that only SPI frames with exactly 32 SCLK falling

edges (32 or 24 if SPI CRC is disabled) are accepted by the

interface as a valid write. SPI frames of lengths other than these

values are ignored and the SCLK_COUNT_ERR flag asserts in

the DIGITAL_DIAG_RESULTS register.

Readback Modes

The AD5758 offers four readback modes, as follows:



Two stage readback mode



Autostatus readback mode



Shared SYNC autostatus readback mode



Echo mode

The two stage readback consists of a write to a dedicated

operation (NOP) command, during which the contents of the

selected register are available on SDO.

Table 13. SDO Contents for Read Operation

MSB

LSB

[D31:D30] D29

[D28:24]

[D23:D8] [D7:D0]

0b10

FAULT pin status Register address

Data

CRC

Bits[D31:D30] = 0b10 are used for synchronization purposes

during readback.

If autostatus readback mode is selected, the contents of the status

This feature allows the user to continuously monitor the status

up with this feature disabled. When this feature is enabled, the

normal two stage readback feature is not available. Only the

status register is available on SDO. To read back any other

following the two stage readback sequence. The automatic

status readback can be reenabled after the register is read back.

The shared SYNC autostatus readback is a special version of the

autostatus readback mode used to avoid SDO bus contention

when multiple devices are sharing the same SYNC line.

Echo mode behaves similarly to autostatus readback mode,

except that every second readback consists of an echo of the

previous command written to the AD5758 (see Figure 82). See

the Reading from Registers section for further details on the

readback modes.

COMMAND

STATUS

CONTENTS

COMMAND

Figure 82. SDO Contents, Echo Mode

WATCHDOG TIMER (WDT)

The WDT feature is useful to ensure that communication is not

lost between the system controller and the AD5758 and that the

SPI datapath lines function as expected.

When enabled, the WDT alerts the system if the AD5758 has not

received a specific SPI frame in the user-programmable timeout

period. When the specific SPI frame is received, the watchdog

resets the timer controlling the timeout alert. The SPI frame

used to reset the WDT is configurable as one of the two

following choices:



A specific key code write to the key register (default).



A valid SPI write to any register.

On a watchdog timeout event, a dedicated WDT_STATUS bit

in the status register, as well as a WDT_ERR bit in the DIGITAL_

DIAG_RESULTS register, alerts the user that the WDT timed

out. Note that, after a WDT timeout occurs, all writes to the

DAC_INPUT register, as well as the hardware or software

LDAC events, are ignored until the active WDT fault flag within

the DIGITAL_DIAG_RESULTS register clears.

After this flag clears, the WDT can be restarted by performing a

subsequent WDT reset command.

On power-up, the WDT is disabled by default. The default

timeout setting is 1 sec. The default method to reset the WDT is

to write one specific key and, on timeout, the default action is to

set the relevant flag bits and the FAULT pin. See Table 40 for the

specific register bit details to support the configurability of the

WDT operation.

USER DIGITAL OFFSET AND GAIN CONTROL

The AD5758 has a USER_GAIN register and a USER_OFFSET

the entire signal chain. The 16-bit USER_GAIN register allows

the user to adjust the gain of the DAC channel in steps of 1 LSB.

The USER_GAIN register coding is straight binary, as shown in

Table 14. The default code in the USER_GAIN register is 0xFFFF,

which results in no gain factor applied to the programmed output.

In theory, the gain can be tuned across the full range of the output.

In practice, the maximum recommended gain trim is approx-

imately 50% of the programmed range to maintain accuracy.

Table 14. Gain Register Adjustment

Gain Adjustment Factor

D15

D14 to D1

65,535/65,536

…

2/65,536

1/65,536

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