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AD5758 Datasheet(PDF) 60 Page - Analog Devices

Part # AD5758
Description  Single-Channel, 16-Bit Current and Voltage Output DAC
PDF  72 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5758 Datasheet(HTML) 60 Page - Analog Devices

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AD5758
Data Sheet
Rev. 0 | Page 60 of 72
Bits
Bit Name
Description
Reset
Access
12
Reserved
Reserved. (Do not alter the default value.)
0x0
R/W
11
INT_I_MONITOR_EN
Enable internal current monitor function.
0x0
R/W
0: disable (default).
1: enable.
10
GLOBAL_SW_LDAC
When enabled, the DUT address bits are ignored when performing a
software LDAC command, enabling multiple devices to be simultaneously
updated using one SW_LDAC command.
0x0
R/W
0: disable (default).
1: enable.
9
FAULT_TIMEOUT
Enable reduced fault detect timeout. This bit configures the delay from when
the analog block indicates a VIOUT fault has been detected to the associated
change of the relevant bit in the ANALOG_DIAG_RESULTS register. This
feature provides flexibility to accommodate a variety of output load values.
0x1
R/W
0: fault detect timeout = 25 ms.
1: fault detect timeout = 6.5 ms (default).
[8:5]
Reserved
Reserved. Do not alter the default value of these bits.
0x0
R/W
4
Reserved
Reserved. Do not alter the default value of this bit.
0x0
R/W
3
Reserved
Reserved. Do not alter the default value of this bit.
0x0
R/W
2
Reserved
Reserved. Do not alter the default value of this bit.
0x0
R/W
1
Reserved
Reserved. Do not alter the default value of this bit.
0x0
R/W
0
Reserved
Reserved. Do not alter the default value of this bit.
0x0
R/W
DC-to-DC Configuration 1 Register
Address: 0x0B, Reset: 0x0B0000, Name: DCDC_CONFIG1
This register is used to configure the dc-to-dc controller mode and enables/disables the VIOUT fault protection switch.
Table 38. Bit Descriptions for DCDC_CONFIG1
Bits
Bit Name
Description
Reset
Access
21
FAULT_PIN_STATUS
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
0x0
R
[20:16]
REGISTER_ADDRESS
Register address.
0x0
R
[15:8]
Reserved
Reserved. Do not alter the default value of this bit.
0x0
R0
7
FAULT_PROT_SW_EN
Enable VIOUT fault protection switch.
0x0
R/W
0: disable, that is, fault protection switch is open (default).
1: enable, that is, fault protection switch is closed.
[6:5]
DCDC_MODE
These two bits configure the dc-to-dc converters.
0x0
R/W
00: dc-to-dc converter powered off (default).
01: DPC current mode. The positive DPC rail tracks the headroom of the current
output buffer.
10: DPC voltage mode. The positive DPC rail is regulated to 15 V with respect to
−VSENSE.
11: PPC current mode. VDPC+ is regulated to a user programmable level between 5.43 V
and 28.48 V (depending on the DCDC_VPROG bits, Bits[4:0]) with respect to −VSENSE.
[4:0]
DCDC_VPROG
DC-to-dc programmed voltage in PPC mode. VDPC+ is regulated to a user programmable
level between 5.43 V (0b00000) and 28.48 V (0b11111), in steps of 0.743 V. VDPC+ is
regulated with respect to −VSENSE. See Table 18 for an important note on the PPC
current mode when selecting the VSENSE buffers as ADC inputs.
0x0
R/W



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