AD5758 datasheet(41/72 Pages) AD

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Data Sheet

AD5758

Rev. 0 | Page 41 of 72

The DAC_OUTPUT register (and ultimately the DAC output)

updates in any of the following cases:



If a write is performed to the DAC_INPUT register with the

hardware LDAC pin tied low, the DAC_OUTPUT register is

updated on the rising edge of SYNC and is subject to the

timing specifications in Table 2.



If the hardware LDAC pin is high and a write to the

DAC_INPUT register occurs, the DAC_OUTPUT register

does not update until a software LDAC instruction is

issued or the hardware LDAC pin is pulsed low.



If a WDT timeout occurs with the CLEAR_ON_WDT_

FAIL bit set, the CLEAR_CODE register contents are

loaded into the DAC_OUTPUT register.



If the slew rate control feature is enabled, the DAC_

OUTPUT register contains the dynamic value of the

DAC as it slews between values.

Note that, while a WDT fault is active, all writes to the DAC_

INPUT register, as well as hardware or software LDAC events,

are ignored. If the CLEAR_ON_WDT_FAIL bit is set such that

the output is set to the clear code, when the WDT fault flag

clears, the DAC_INPUT register must be written to before an

update to the DAC_OUTPUT register occurs; that is, performing a

software or hardware LDAC only reloads the DAC with the clear

code. As described in the section, after configuring the DAC

range via the DAC_CONFIG register, a write to the DAC_

INPUT register must occur, even if the contents of the DAC_

INPUT register are not changing from their current value.

The GP_CONFIG2 register contains a bit to enable a global

software LDAC mode, whereby the DUT address bits of the

SW_LDAC command are ignored, thus enabling multiple

AD5758 devices to be simultaneously updated using a single

SW_LDAC command. This feature is useful if the hardware

LDAC pin is not being used in a system containing multiple

AD5758 devices.

DAC Data Integrity Diagnostics

To protect against transient changes to the internal digital

circuitry, the digital block stores both the digital DAC value and

an inverted copy of the digital DAC value. A check is completed

to ensure that the two values correspond to each other before

the DAC is strobed to update to the DAC code. This feature is

enabled by default via the INVERSE_DAC_CHECK_EN bit in

the DIGITAL_DIAG_CONFIG register.

Outside of the digital block, the DAC code is stored in latches,

as shown in Figure 84. These latches are potentially vulnerable

to the same transient events as those protected against within

the digital block. To protect the DAC latches against such

transients, the DAC latch monitor feature can be enabled via

the DAC_LATCH_MON_EN bit within the DIGITAL_DIAG_

CONFIG register. This feature monitors the actual digital code

driving the DAC and compares it with the digital code generated

within the digital block. Any difference between the two codes

causes the DAC_LATCH_MON_ERR flag to be set in the

DIGITAL_DIAG_RESULTS register.

16-BIT

DAC

DIGITAL

BLOCK

DAC LATCHES

Figure 84. DAC Data Integrity

USE OF KEY CODES

Key codes (via the key register) are used for the following

functions (see the Key Register section for full details):



Initiate calibration memory refresh.



Initiate a software reset.



Initiate a single ADC conversion.



WDT reset key.

Using specific keys for initiating such actions as a calibration

memory refresh or a device reset provides extra system

robustness because it reduces the probability of either of these

tasks being initiated in error.

SOFTWARE RESET

A software reset requires two consecutive writes to the key register,

0x15FA and 0xAF51, respectively. A reset of the device can be

initiated via the hardware RESET pin, the software reset keys, or

automatically after a WDT timeout (if configured to do so). The

RESET_OCCURRED bit in the DIGITAL_DIAG_RESULTS

power-up. Both of the diagnostic results registers implement a

write 1 to clear feature; that is, a 1 must be written to this bit to

clear it (see the Sticky Diagnostic Results Bits section).

CALIBRATION MEMORY CRC

For every calibration memory refresh cycle (which is initiated

via a key code write to the key register or automatically initiated

when the range bits, Bits[3:0] of the DAC_CONFIG register, are

changed), an automatic CRC is calculated on the contents of the

calibration memory shadow registers. The result of this CRC is

compared with the factory stored reference CRC value. If the

CRC values match, the read of the entire calibration memory is

considered valid. If they do not match, the CAL_MEM_CRC_ERR

bit in the DIGITAL_DIAG_RESULTS register is set to 1. This

feature is enabled by default and can be disabled via the CAL_

MEM_CRC_EN bit in the DIGITAL_DIAG_CONFIG register.

While this calibration memory refresh cycle is active, two stage

readback commands are permitted, but a write to any register

(other than the TWO_STAGE_READBACK_SELECT register

or the NOP register) causes the INVALID_SPI_ACCESS_ERR

bit in the DIGITAL_DIAG_RESULTS register to set. As described

in the section, a wait period of 500 μs is recommended after a

calibration memory refresh cycle is initiated.

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