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AD9174 Datasheet(PDF) 134 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 134 Page - Analog Devices

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AD9174
Data Sheet
Rev. A | Page 134 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x473
INIT_LANE_SYNC
7
ILS7
Initial lane synchronization status for Lane 7.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
6
ILS6
Initial lane synchronization status for Lane 6.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
5
ILS5
Initial lane synchronization status for Lane 5.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
4
ILS4
Initial lane synchronization status for Lane 4.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
3
ILS3
Initial lane synchronization status for Lane 3.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
2
ILS2
Initial lane synchronization status for Lane 2.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
1
ILS1
Initial lane synchronization status for Lane 1.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0
ILS0
Initial lane synchronization status for Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0x475
CTRLREG0
[7:4]
RESERVED
Reserved.
0x0
R/W
3
SOFTRST
QBD soft reset. Active high synchronous
reset. Resets all hardware to power-on
state. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
2
FORCESYNCREQ
Command from application to assert a
synchronization request. Active high. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R/W
1
RESERVED
Reserved.
0x0
R
0
REPL_FRM_ENA
When this level input is set, it enables the
replacement of frames received in error.
This control is paged by the LINK_PAGE
control in Register 0x300. This signal must
only be programmed while the QBD is
held in soft reset (Register 0x475, Bit 3), and
must not be changed during normal
operation.
0x1
R/W



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