AD9174 datasheet(139/164 Pages) AD

139 / 164 page

Data Sheet

AD9174

Rev. A | Page 139 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x487

ECNT_CTRL7

[7:6]

RESERVED

Reserved.

0x0

[5:3]

ECNT_ENA7

Error counter enables for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7

R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0]

ECNT_RST7

Reset error counters for Lane 7. This

control is paged by the LINK_PAGE control

in Register 0x300. Counters of each lane

are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x488

ECNT_TCH0

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH0

Terminal count hold enable of error counters

for Lane 0. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x489

ECNT_TCH1

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH1

Terminal count hold enable of error counters

for Lane 1. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

AD9174 Datasheet(PDF) 139 Page - Analog Devices

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