AD9174 datasheet(140/164 Pages) AD

140 / 164 page

AD9174

Data Sheet

Rev. A | Page 140 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x48A

ECNT_TCH2

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH2

Terminal count hold enable of error counters

for Lane 2. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x48B

ECNT_TCH3

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH3

Terminal count hold enable of error counters

for Lane 3. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

0x48C

ECNT_TCH4

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH4

Terminal count hold enable of error counters

for Lane 4. This control is paged by the

LINK_PAGE control in Register 0x300.

When set, the designated counter is to

hold the terminal count value of 0xFF

when it is reached until the counter is

reset by the user. Otherwise, the

designated counter rolls over. Counters of

each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while

the QBD is held in soft reset (Register 0x475,

Bit 3), and must not be changed during

normal operation.

AD9174 Datasheet(PDF) 140 Page - Analog Devices

AD9174 Datasheet(HTML) 140 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL