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TMS28F033 Datasheet(PDF) 32 Page - Texas Instruments |
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TMS28F033 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 52 page  TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over recommended ranges of supply voltage and ambient temperature range, synchronous read operations (see Figure 11, Figure 14, and Figure 21) PARAMETER 3.3-V VDDE RANGE 5-V VDDE RANGE UNITS MIN MAX MIN MAX tCLK CLK period (see Note 25) ns tCH High time, clock 10 10 ns tCL Low time, clock 10 10 ns tCLCH Rise time, CLK 3 4 ns tCHCL Fall time, CLK 3 4 ns tCHAX Hold time, address from CLK high 3 3 ns tCHRL Hold time, WR from CLK high 3 3 ns tCHLH Hold time, LBA from CLK high 5 5 ns tCHBH Hold time, BAA from CLK high TBD TBD ns tCHGH Hold time, OE from CLK high 2 2 ns tCHSH Hold time, DIS from CLK high 2 2 ns tELCH Setup time, E to CLK high TBD TBD ns tAVCH Setup time, address to CLK high 10 10 ns tRHCH Setup time, WR to CLK high 0 0 ns tLLCH Setup time, LBA to CLK high 6 6 ns tBLCH Setup time, BAA to CLK high TBD TBD ns tGLCH Setup time, OE to CLK high 9 9 ns tSLCH Setup time, DIS to CLK high 12 12 ns DCR7:6 = 00 47 47 ns tCHCH1 LBA/CLK high to data latched (OE/CLK), for one wait-state access DCR7:6 = 01 43 43 ns DCR7:6 = 1X 40 40 ns tCHQD OE/CLK high to data bus driven 0 0 ns DCR7:6 = 00 22 TBD ns tCHQV OE/CLK high to data valid DCR7:6 = 01 26 TBD ns DCR7:6 = 1X 29 TBD ns tCHQX CLK high to data invalid 5 5 ns tCHQZ CLK high to data high Z (see Note 26) 40 40 ns tCHQL CLK high to QV low TBD TBD ns tCHQH CLK high to QV high TBD TBD ns NOTES: 25. tCLK min = max ((tCHCH1 / #ws), tCHQV + tdsu,cpu +tsys) where: tdsu,cpu = data setup time for CPU tsys = system margin #ws = number of wait states (CLKs) from address latched to data latched 26. IOL/IOH = ± 4 mA, value dependent on loading conditions |
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