VPPL

VPPH

18

17

16

15

14

13

12

11

XXXXXh

FFh

9

8

7

5

3

PA

46

2

1

XXXXXh

CLK

A–1–A16 (word-wide)

A0–A16 (double-word-

wide)

E

WR

Asynchronous WE

Data

LBA

BAA

OE

RY/BY

QV

DQ0–DQ7 and

DQ24–DQ31

(word-wide)

DQ0–DQ31

(double-word-wide)

VPP

RP

40h or 04h

10

Valid SR

tWHYH1, 2

tVHWH

tWHDX

tDVWH

tYHVL

tWH

tWHWH

tWL

tAVWH

tWHAX

tWHEH

tELWL

Write Program-

Setup Command

Write Valid

Address and Data

Automated Word/

Double-Word

Programming

Read Status-

Register Bits

Write Read-Array

Command

Hi-Z

Hi-Z

Hi-Z

tWHYL

BASIC/ENHANCED

PIN SET

DCR0

OE

MODE

DCR1

WE

MODE

DCR2

DIS/WORD

DCR3

LRV/BAA

DCR4

BURST

LENGTH

DCR25,24

BURST

LATENCY (X)

DCR29,28

BURST

LATENCY (Y)

DCR30

x16 WRITE

OPTION

DCR31

Basic pin set (DCR0 = 0)

0

1

(see Note D)

Optional

X

(see Note E)

XX

XX

X

0

(see Note F)

Enhanced pin set (DCR0 = 1)

0

1

(see Note D)

Optional

X

(see Note E)

XX

XX

X

0

(see Note F)

NOTES: A. X is a don’t care. PA is the address to be programmed.

B. See Table 8 for DCR setting descriptions.

C. For asynchronous writes, the address and data/command are latched on the WE rising edge.

D. For synchronous two-cycle write timing (DCR2 = 0), see Figure 22.

E. For LRV usage (DCR4 = 0), see Figure 4; and for DCR4 = 1, see Figure 5.

F. When using the 16-bit data bus (DCR3 = 1 and WORD = VIL), both two-cycle writes (DCR31 = 0) and three-cycle writes (DCR31 = 1) are available. For

asynchronous three-cycle writes, the “write valid address and data” cycle is repeated for the second 16-bit data segment.

Figure 23. Asynchronous Write-Cycle Timing (Two-Cycle Write) With Device Configuration Register Settings

ADVANCE INFORMATION