TMS28F033 datasheet(10/52 Pages) TI

10 / 52 page

TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

command definition (continued)

Table 6. Algorithm Selection Codes (See Note 2)

DATA BUS WIDTH

ADDRESS

(A0 – A16)

A–1

DATA OUT

X0h

VIL

Manufacturer Code

0097h

16-Bit

(see Note 3)

X1h

VIL

VIH

Device Code

0068h

X2h

VIH

VIL

DCR Value

DDDDh

X0h

VIL

—

Manufacturer Code

00000097h

32-Bit

(see Note 4)

X1h

VIL

VIH

—

Device Code

00000068h

X2h

VIH

VIL

—

DCR Value

DD0000DDh

NOTES:

X is a don’t care.

3. When using the 16-bit data bus, the data lines are DQ0 – DQ7 and DQ23 – DQ31.

4. When using the 32-bit data bus, the data lines are DQ0 – DQ31.

status register

The status register allows the user to determine whether the state of a program/erase operation is pending or

complete. The status register is monitored by writing a read-status command to the CSM and reading the

resulting status code on I/O pins DQ0 – DQ7. This operation is valid in either the word-wide (x16) or

double-word-wide (x32) mode. The high-order I/Os (DQ8 – DQ31) are set to 000000h internally.

After a read-status command has been given, the data appearing on DQ0 – DQ7 remains as status register data

until a new command is issued to the CSM. To return the device to other modes of operation, a new command

must be issued to the CSM. Status register data is updated on every clock cycle. During periods when the WSM

is active, the status register can be read to determine the WSM status. Table 7 defines the status-register bits

and their functions.

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