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TMS28F033 Datasheet(PDF) 34 Page - Texas Instruments |
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TMS28F033 Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 52 page ![]() TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY SMJS833 – NOVEMBER 1997 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and ambient temperature range, asynchronous write/erase operations (see Figure 23 and Figure 26) 3.3-V VDDE RANGE 5-V VDDE RANGE UNITS MIN MAX MIN MAX tWHWH Cycle time, write TBD TBD ns tWHAX Hold time, address from WE high TBD TBD ns tYHVL Hold time, VPP from RY/BY high 0 0 ns tWHEH Hold time, E from WE high TBD TBD ns tAVWH Setup time, address to WE high TBD TBD ns tELWL Setup time, E to WE low TBD TBD ns tVHWH Setup time, VPP to WE high TBD TBD ns tWL Pulse duration, WE low TBD TBD ns tWH Pulse duration, WE high TBD TBD ns tDVWH Data valid to WE high TBD TBD ns tWHDX WE high to data invalid TBD TBD ns tWHYH1 Duration of double-word/word operation TBD TBD ns tWHYH2 Duration of double-word/word operation in low-power programming (LPP) mode TBD TBD ns tWHYH3 Duration of block-erase operation TBD TBD ns tWHYH4 Duration of block-erase operation in LPP mode TBD TBD ns tWHYL WE high to RY/BY low TBD TBD ns VDDI power-up and reset/power-down (RP) characteristics over recommended ranges of supply voltage and ambient temperature range (see Figure 12) PARAMETER MIN MAX UNITS t5HPH Power (VDDI) applied to RP high 1 ms tPHCH RP high to LBA/CLK high 200 ns tPL5L RP low to power (VDDI) low 0 ns t5HVH VDDI high to VPP high 500 ns tVHPH VPP high to RP high 100 ns |
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