TMS28F033 datasheet(4/52 Pages) TI

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TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions

TERMINAL

DESCRIPTION

NAME

TYPE†

DESCRIPTION

A–1

Word select address. A–1 is the low-order address for the 16-bit data bus, and selects between the high and low word.

A–1 is not used for the 32-bit data bus.

A0 – A16

Address bus. A0 – A16 select one of the 131 072 32-bit segments (double-words), or, with A–1, selects one of the

262 144 16-bit segments (words). A0 is the low-order address for the 32-bit data bus.

DQ0 – DQ31

I/O

Data bus. Bidirectional data bus, where for both 16-bit and 32-bit data bus widths, DQ31 is the most significant bit

(MSB) and DQ0 is the least significant bit (LSB). The 16-bit data bus uses DQ0 – DQ7 and DQ24 – DQ31.

LBA

Load-burst address. For synchronous operation, when LBA = VIL on a rising CLK edge, the address is latched for the

beginning of a read or write operation.

BAA

Burst-address advance. When BAA = VIL, the burst state machine increments the burst address for each required

data beat on the rising CLK edge. For BAA usage, see Table 8 and Table 9.

Reset/power-down. When RP = VIL, the device terminates any current-state-machine activity and does not respond

to read requests and does not accept write commands. On the rising edge of RP, the device sets/clears the OBEB

status register bit (SB1) based on the status of VPP. WhenVPPwVPPH,OBEBisset;ifVPPvVPPL,OBEBiscleared

(see Table 3).

Chip enable. When E = VIL, the device is enabled for read or write operations. When E = VIH, the device is in standby

mode. E is an asynchronous signal. For E usage, see Table 8 and Table 9.

Output enable. OE is used for read operations and can be either synchronous or asynchronous (see Table 8 and

Table 9). For synchronous OE, when OE = VIL on a rising CLK edge, the output data is latched and becomes valid

prior to the next rising CLK edge. OE = VIH during write operations.

LBO

Linear-burst order. When LBO= VIL, the address counter is set for linear burst. When LBO = VIH, the address counter

is set for interleaved burst. For LBO usage, see Table 9 and Table 12.

Write. WR is a synchronous signal that controls the read and write operations. If WR = VIL when the address is latched

(LBA = VIL), then the cycle is a write cycle . If WR = VIH when the address is latched, then the cycle is a read cycle.

Write enable. WE is used for write/erase operations and can be either synchronous or asynchronous (see Table 8

and Table 9). For synchronous WE usage, with the first occurrence of WE = VIL (after the address is latched with LBA

and WR = VIL) on a rising CLK edge, the input data/command is latched. For asynchronous writes, the data and

address are latched on the WE rising edge.

WORD

Word enable. WORD is used for selection of the data bus width. When WORD = VIL, the device has a 16-bit data bus,

and data is input or output on DQ0 – DQ7 and DQ24 – DQ31, and address A–1 selects between the high and low word.

When WORD = VIH, the device has a 32-bit data bus and turns off the A–1 input buffer. For WORD usage, see Table 8

and Table 9.

DIS

Disable output. When DIS = VIL, the synchronous OE, DQ’s, and QV signals are disabled. DIS functions as an

additional synchronous output enable (opposite in logic to OE). For DIS usage, see Table 8 and Table 9.

LRV

Low regulator voltage. When LRV = VIL during a write/erase operation, the LRVS status register bit (SB4) is set

(see Table 7). LRV is an asynchronous signal. For LRV usage, see Table 8 and Table 9.

Data valid. QV is used for read operations. QV = VIL when output data is valid on the data bus for either a single or

burst-read operation. When QV = VIH, there is no valid data on the data bus. For QV usage, see Table 8 and Table 9.

RY/BY

Ready/busy. RY/BY indicates the status of the WSM. When RY/BY = VIL, the WSM is currently active performing an

operation. When RY/BY = VIH, the WSM is ready for a new operation. For RY/BY usage, see Table 8 and Table 9.

CLK

Clock. Signals on both the address and data buses are transmitted and received relative to this system clock. All

synchronous inputs must meet setup and hold times relative to the rising CLK edge.

3/5IO

3.3/5.0 I/O select. 3/5IO is used to select the external power supply, VDDE, as either 3.3 V or 5 V. Set 3/5IO = VIH for

VDDE = 3.3 V operation, and set 3/5IO = VIL for VDDE = 5 V operation. For 3/5IO usage, see Table 8 and Table 9.

† I = input, O = output, OD = open drain, S = power supply

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