TMS28F033 datasheet(25/52 Pages) TI

25 / 52 page

TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

BUS

OPERATION

COMMAND

COMMENTS

Write

Write program

setup

Data = 40h for main array or 04h for

overlay block

Addr = 00000h for synchronous WE

or XXXXXh for

asynchronous WE

Write

Data = First x16 word to be

programmed

Addr = A–1 (see Table 3)

Write

Data = Second x16 word to be

programmed

Addr = Address of x16 word to be

programmed

Read

Status-register data. Status register is

updated on each rising clock.

Wait

Check SB7

1 = Ready, 0 = Busy

Repeat for subsequent words.

Write read-array command after the last word-program operation to

reset the device to read-array mode.

BUS

OPERATION

COMMAND

COMMENTS

Wait

Check SB3

Detect VPP low

(see Note B)

Wait

Check SB4

Word-program error

(see Note C)

NOTES: A. Full status-register check can be done after each word or after a sequence of words.

B. SB3 must be cleared before attempting additional program / erase operations.

C. SB4 is cleared only by the clear-status-register command, but this does not prevent additional program operation attempts.

Figure 7. Automated x16 Word-Programming Flowchart With Three-Cycle Write (DCR4 = 1)

Start

Issue Program-Setup

Command and Address

Issue First x16 Word

Data and Address A–1

Read Status-Register

Bits

SB7 = 1

Yes

Full Status-Register

Check (optional)

Word-Program Completed

Read Status-Register Bits

SB3 = 0

VPP Range Error

Word-Program Failed

Yes

Word-Program Passed

SB4 = 0

FULL STATUS-REGISTER-CHECK FLOW

Issue Second x16 Word

Data and Address

See Note A

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