Automated

Word/Double-

Word

Programming

E

(word-wide)

A0–A16

(double-word-wide)

WR

WE

LBA

OE

BAA

DQ0–DQ7 and DQ24–DQ31

(word-wide)

DQ0–DQ31

(double-word-wide)

QV

RY/BY

00000h

PA

00000h

RP

CLK

40h or 04h

Valid SR

FFh

Hi-Z

Hi-Z

Hi-Z

Write

Program-Setup

Command

Write Valid

Address and

Data

Read Status

Register Bits

18

11

12

13

14

15

16

17

6

4

3

5

789

12

10

Data

Write

Read-Array

Command

BASIC/ENHANCED

PIN SET

DCR0

OE

MODE

DCR1

WE

MODE

DCR2

DIS/WORD

DCR3

LRV/BAA

DCR4

BURST

LENGTH

DCR25,24

BURST

LATENCY (X)

DCR29,28

BURST

LATENCY (Y)

DCR30

x16 WRITE

OPTION

DCR31

Basic pin set (DCR0 = 0)

0

0

(see Note D)

Optional

X

(see Note E)

XX

XX

X

0

(see Note F)

Enhanced pin set (DCR0 = 1)

0

0

(see Note D)

Optional

X

(see Note E)

XX

XX

X

0

(see Note F)

NOTES: A. X is a don’t care. PA is the address to be programmed.

B. See Table 8 for DCR setting descriptions.

C. Wait states can be inserted between the address and data phases of a command or write-data cycle. In addition, the address phase of the write-data cycle can

occur on the same CLK as the data phase of the command cycle (see Figure 24).

D. For asynchronous two-cycle write timing (DCR2 = 1), see Figure 23.

E. For LRV usage (DCR4 = 0), see Figure 3, and for DCR4 = 1, see Figure 5.

F. When using the 16-bit data bus (DCR3 = 1 and WORD = VIL), both two-cycle writes (DCR31 = 0) and three-cycle writes (DCR31 = 1) are available. For synchronous

three-cycle write timing, see Figure 24.

Figure 22. Synchronous Write-Cycle Timing (Two-Cycle Write) With Device Configuration Register Settings

ADVANCE INFORMATION