TMS28F033 datasheet(36/52 Pages) TI

36 / 52 page

910

A–1 – A16 (word-wide)

A0–A16

(double-word-wide)

LBA

BAA

DQ0–DQ7 and DQ24–DQ31

(word-wide)

DQ0–DQ31 (double-word-wide)

RY/BY

VDDI/VDDE

CLK

BASIC/ENHANCED

PIN SET

DCR0

MODE

DCR1

MODE

DCR2

DIS/WORD

DCR3

LRV/BAA

DCR4

BURST

LENGTH

DCR25,24

BURST

LATENCY (X)

DCR29,28

BURST

LATENCY (Y)

DCR30

x16 WRITE

OPTION

DCR31

Basic pin set (DCR0 = 0)

(see Note D)

Optional

(see Note E)

Enhanced pin set (DCR0 = 1)

(see Note D)

Optional

(see Note E)

NOTES: A. X is a don’t care.

B. See Table 8 through Table 12 for DCR setting descriptions.

C. Burst doesn’t occur while LBA is low.

D. Synchronous and asynchronous OE are available (see Figure 20); DCR1 = 0 and DCR1 = 1, respectively.

E. For DIS usage, see Figure 21.

Figure 13. Asynchronous Read Cycles With Device Configuration Register Settings

ADVANCE INFORMATION

TMS28F033 Datasheet(PDF) 36 Page - Texas Instruments

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