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TMS28F033 Datasheet(PDF) 33 Page - Texas Instruments

Part # TMS28F033
Description  4194304-BIT SYNCHRONOUS FLASH MEMORY
PDF  52 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS28F033 Datasheet(HTML) 33 Page - Texas Instruments

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TMS28F033
4194304-BIT
SYNCHRONOUS FLASH MEMORY
SMJS833 – NOVEMBER 1997
33
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
switching characteristics over recommended ranges of supply voltage and ambient temperature
range, synchronous reads with asynchronous OE operations (see Figure 20)
PARAMETER
3.3-V VDDE
RANGE
5-V VDDE
RANGE
UNITS
MIN
MAX
MIN
MAX
tGLQD
OE low to data bus driven
0
0
ns
DCR[7:6] = 00
TBD
TBD
ns
tGLQV
OE low to data valid
DCR[7:6] = 01
TBD
TBD
ns
DCR[7:6] = 1X
TBD
TBD
ns
tGHQX
OE high to data invalid
TBD
TBD
ns
tGHQZ
OE high to data high Z
TBD
TBD
ns
timing requirements over recommended ranges of supply voltage and ambient temperature range,
synchronous write/erase operations (see Figure 22, Figure 24, and Figure 25)
3.3-V VDDE
RANGE
5-V VDDE
RANGE
UNITS
MIN
MAX
MIN
MAX
tCHEH
Hold time, E from CLK high
TBD
TBD
ns
tCHRH
Hold time, WR from CLK high
3
3
ns
tCHWH
Hold time, WE from CLK high
2
2
ns
tCHDX
Hold time, CLK high to data
3
3
ns
tYHVL
Hold time, VPP from RY/BY high
0
0
ns
tCHYH1
Duration of double-word/word write operation
TBD
TBD
TBD
TBD
ns
tCHYH2
Duration of double-word/word write operation in low-power programming (LPP)
mode
TBD
TBD
TBD
TBD
ns
tCHYH3
Duration of block-erase operation
TBD
TBD
TBD
TBD
ns
tCHYH4
Duration of block-erase operation in LPP mode
TBD
TBD
TBD
TBD
ns
tELCH
Setup time, E to CLK high
TBD
TBD
ns
tRLCH
Setup time, WR to CLK high
10
10
ns
tWLCH
Setup time, WE to CLK high
9
9
ns
tDVCH
Setup time, data to CLK high
10
10
ns
tVHCH
Setup time, VPP to LBA/CLK high
TBD
TBD
ns
tCHYL
CLK high to RY/BY low
TBD
TBD
ns



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