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TMS28F033 Datasheet(PDF) 49 Page - Texas Instruments

Part # TMS28F033
Description  4194304-BIT SYNCHRONOUS FLASH MEMORY
PDF  52 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS28F033 Datasheet(HTML) 49 Page - Texas Instruments

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XXXXXh
18
11
12
13
14
15
16
17
6
4
3
5
78
9
12
10
XXXXXh
VPPH
VPPL
Hi-Z
FFh
BBA
CLK
A–1–A16
(word-wide)
A0–A16
(doble-word-wide)
E
Asynchronous WE
WR
D0h or 0Dh
20h or 02h
Hi-Z
BAA
LBA
OE
RY/BY
QV
Hi-Z
DQ0–DQ7 and
DQ24–DQ31
(word-wide)
DQ0–DQ31
(double-word-wide)
VPP
RP
Valid SR
tWHYH3, 4
Write
Erase-Setup
Command
Write
Erase-Confirm
Command
Automated Erase
Read Status
Register Bits
Write Read-
Array Command
BASIC/ENHANCED
PIN SET
DCR0
OE
MODE
DCR1
WE
MODE
DCR2
DIS/WORD
DCR3
LRV/BAA
DCR4
BURST
LENGTH
DCR25,24
BURST
LATENCY (X)
DCR29,28
BURST
LATENCY (Y)
DCR30
x16 WRITE
OPTION
DCR31
Basic pin set (DCR0 = 0)
0
1
(see Note D)
Optional
X
(see Note E)
XX
XX
X
X
Enhanced pin set (DCR0 = 1)
0
1
(see Note D)
Optional
X
(see Note E)
XX
XX
X
X
NOTES: A. X is a don’t care. BBA is the block base address.
B. See Table 8 for DCR setting descriptions.
C. For asynchronous erase, the address and command are latched on the WE rising edge.
D. For asynchronous erase-cycle timing (DCR2 = 1), see Figure 25.
E. For LRV usage (DCR4 = 0), see Figure 8; and for DCR4 = 1, see Figure 9.
Figure 26. Asynchronous Erase-Cycle Timing With Device Configuration Register Settings
ADVANCE INFORMATION



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