TMS28F033 datasheet(19/52 Pages) TI

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TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

clear status register

For DCR4 = 0 (LRV usage), the WSM can set the VPP status bit (SB3), the low-regulator-voltage status bit (SB4),

and the operation status bit (SB5). For DCR4 = 1, the WSM can set the VPP status bit (SB3), the program status

bit (SB4), and the erase status bit (SB5) of the status register. The clear-status-register command (50h) allows

the external microprocessor to clear SB3, SB4, and SB5. When the status bits are cleared, the device returns

to the read-array mode.

load device configuration register

The load DCR command is a two-bus-cycle command that loads the device configuration register. When the

DCR load command (96h) is written to the CSM, the CSM will set up the device configuration register to be

loaded on the next write cycle. On the second cycle, the configuration data DDDDh loads the two bytes of the

device configuration register DCR0 – DCR7 and DCR24 – DCR31 (see Table 5 and Table 6). DCR8 – DCR23

and DCR26 – DCR27 are reserved and should be loaded with 0s.

read operations

There are three read operations available: read array, read algorithm-selection code, and read status register.

See Table 13 and Table 14 for the required control signals needed with synchronous reads.

D Read array

The read-array command consists of two bus cycles, and is listed in Table 5. For synchronous reads on the

first bus cycle, the CSM command code FFh on DQ0 – DQ7 and the address 00000h are entered.

The second bus cycle begins with the address phase where, for synchronous operation, LBA goes low on a

rising clock edge. On the same clock (CLK 1 of Figure 14 for burst reads, or CLK 1 of Figure 27 for single

reads), the address is latched and WR is sampled. For a read, WR is set high, and the device is ready for the

read-data phase. The data phase follows the address phase by one or more clock cycles, where OE goes

low on a rising clock edge and the data is driven onto the bus DQ0 – DQ31 for x32, and DQ0 – DQ7 with

DQ24 – DQ31 for x16. For single reads, the data is valid for CLK 3 (see Figure 27). For burst reads, on CLK 3

of Figure 14, BAA is brought low to burst the second data segment. OE is kept low for four clock cycles

(CLKs 2–5) and BAA is kept low for three CLKs (CLKs 3 – 5), which bursts four words for MOD4. Burst reads

for burst lengths MOD8, MOD16, or MOD32 are accomplished by holding OE and BAA low for each data

segment in the same way (see Figure 14 through Figure 21). The optional output valid (QV) goes low when

valid data is output from the device (see the Terminal Functions table, Figure 14 through Figure 21, and

Figure 27).

D Read algorithm-selection code

As listed in Table 5, CSM command code 90h is written on DQ0 – DQ7. Two bus cycles are required for this

operation: the first to enter the command code and a second to read the manufacturer/device code or DCR

value by loading the required A1A0 address bits (see Table 5 and Table 6). By loading a new address, the

manufacturer-equivalent code is obtained on DQ0 – DQ7 with both A1 and A0 at a logic-level VIL. Similarly,

the device-equivalent code is obtained when A1 is set to VIL and A0 is set to VIH. The device configuration

D Read status register

The status register is read by entering the command code 70h on DQ0 – DQ7. Two bus cycles are required

for this operation: one to enter the command code and a second to read the status register (see Table 5).

The status register contents are updated on every clock cycle.

The device interface is synchronous but supports asynchronous read timings, which hold the address valid and

LBA low throughout the address and data phases as required by some microprocessors after power-up (see

Figure 13).

TMS28F033 Datasheet(PDF) 19 Page - Texas Instruments

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