TMS28F033 datasheet(20/52 Pages) TI

20 / 52 page

TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

programming operations

There

are

two

program

operations

available:

program-setup/program

main

array

and

program-setup/program to overlay block. Both are available with synchronous or asynchronous writes.

Both the x16 and x32 data bus configurations have a two-bus-cycle write capability, where in two bus cycles,

either one 16-bit word or one 32-bit word is programmed, respectively. In addition, three-cycle writes are

available with the 16-bit data bus by configuring DCR31(see Table 8). On the first cycle, which is the command

cycle, the CSM command code 40h or 04h is loaded to set up the device for programming either to the main

array or to the overlay block array, respectively. On the second cycle, which is the write-data cycle, the data is

loaded. After the desired command code and data are loaded, the WSM takes over and correctly sequences

the device to complete the program operation. During this time, the CSM responds only to status reads until

the program operation has been completed, after which all commands to the CSM become valid again. Once

a program command has been issued, the WSM cannot normally be interrupted until the program algorithm is

completed. Monitoring of the write operation is possible through the status register or the ready/busy (RY/BY)

pin (see Figure 22 and Figure 24). See Figure 22 and Figure 24 for two- and three-cycle synchronous writes

respectively. For asynchronous writes, the address and command/data are latched on the rising edge of WE

(see Figure 23 for asynchronous write).

Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain

VPP ≥ VPPH (see Figure 22 and Figure 23). Only 0s are written and compared during a program operation. If

1s are programmed, the memory cell contents do not change and no error occurs.

A program-setup command can be aborted by writing FFFFh on DQ0 – D7 and DQ24 – DQ31 (in word-wide

mode), or FFFFFFFFh (in double-word-wide mode) during the second cycle. After writing all 1s during the

second cycle, the CSM responds only to status reads. When the WSM status bit (SB7) is set to a logic-high level,

signifying the nonprogram operation is terminated, all commands to the CSM become valid again.

erase operations

There are two erase operations that can be performed: block-erase-setup/confirm main array (20h/D0h) and

block-erase-setup/confirm overlay block (02h/0Dh). An erase operation must be used to initialize all bits in an

array block to 1s. After block-erase confirm is issued, the CSM responds only to status reads until the WSM

completes its task. Both of these erase operations are available with synchronous and asynchronous writes.

Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is

accomplished only by blocks; data at single address locations within the array cannot be individually erased.

The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a

command sequence to the CSM: block-erase setup (20h/02h) followed by block-erase confirm (D0h/0Dh) (see

Figure 25 and Figure 26). This two-command erase sequence protects against accidental erasure of memory

contents.

Asynchronous erase-setup and confirm commands are latched on the rising edge of WE, and block addresses

are latched during the block-erase-confirm command on the rising edge of WE. For both synchronous and

asynchronous operations, when the block-erase-confirm command is complete, the WSM automatically

executes a sequence of events to complete the block erasure. During this sequence, the block is programmed

with logic 0s, data is verified, all bits in the block are erased, and verification is performed to ensure that all bits

are correctly erased. Monitoring of the erase operation is possible through the status register or the ready/busy

(RY/BY) pin (see Figure 25 and Figure 26).

Taking RP to VIL during erasing aborts the erase operation. During erasing, VPP must remain VPP>=VPPH as

seen in Figure 25 and Figure 26.

TMS28F033 Datasheet(PDF) 20 Page - Texas Instruments

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