TMS28F033 datasheet(15/52 Pages) TI

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TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

burst access and burst performance (continued)

Table 11. Burst Performance (Clock Cycles to Read)

x16 Mode

x32 Mode

FREQUENCY (MHz)

LINEAR†

INTERLEAVE

LINEAR

A–1 = 0

A–1 = 1

INTERLEAVE

LINEAR

< 25 (see Note 9)

4–2– ...–2

< 33 (see Note 9)

4–2– ...–2

5–1– ...–1

4–1– ...–1

4–2– ...–2

< 40 (see Notes 9 and 10)

—

5–2– ...–2

† The state of A–1 when the address is latched (at CLK 1 in Figure 14)

NOTES:

9. The

Y-latency

notation

for

MOD4

has

three

1s/2s

(–1–1–1/–2–2–2).

For

MOD8,

there

are

seven

1s/2s

(–1–1–1–1–1–1–1/–2–2–2–2–2–2–2). MOD16 has fifteen 1’s/2’s, and MOD32 has 31 1’s/2’s.

10. To obtain 5–2– . . . –2 (40 MHz), the required DCR settings are 4–2– . . . –2, and asynchronous OE with BAA-controlled burst.

burst suspend/resume

Burst suspension is the ability to hold the address advance and the data on the output I/Os DQ0 – DQ7 and

DQ24 – DQ31 if in x16 mode, or on DQ0 – DQ31 if in x32 mode. For DCR4 = 1, the suspension of a burst

sequence is possible by bringing BAA high. To resume the burst, bring BAA low again (see Figure 18). When

DCR4 = 0, the suspension of the burst is possible by bringing OE high. To resume the burst, bring OE low again.

linear burst order (LBO)

When performing a burst read, a single starting address is entered into the device and then the TMS28F033

internally accesses a sequence of locations based on that starting address. The burst sequence is determined

by the linear burst order (LBO) setting (see the Terminal Functions table). When LBO = VIL, the burst order is

linear 0–1–2–3....; and when LBO = VIH, the burst order is interleave (see Table 12). Linear burst order is

available with MOD4, MOD8, MOD16, and MOD32. Interleave burst order is available only with MOD4, and only

with the 16-bit data bus.

Table 12. 2-Bit Linear and Interleaved-Burst Sequences (MOD4)

ADDRESS

BURST

A1 – A0 For x32 Mode, AND A0 – A–1 For x16 Mode

BURST

SEQUENCE

DECIMAL

BINARY

START

2ND

3RD

4TH†

START

2ND

3RD

4TH†

Linear

(see Note 11)

Interleave

(see Note 12)

† Burst sequence continues until OE or BAA is brought high.

NOTES: 11. Linear burst is available with both x16 and x32 for MOD4, MOD8, MOD16, and MOD32. For linear burst set LBO=VIL.

12. Interleaved burst is available only with MOD4, and only with the 16-bit data bus. For interleave burst set LBO =VIH.

word (X16) write option

DCR31 determines the number of write cycles for word-wide programming. For DCR31 = 0, the device performs

two-cycle writes, or with DCR31 = 1, the device performs three-cycle writes (see Table 5). See Figure 22 and

Figure 24 for synchronous two- and three-cycle writes, respectively. For asynchronous two-cycle writes, see

Figure 23.

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