TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

12

POST OFFICE BOX 1443

device configuration defaults

The term “default” denotes the state of a bit in the DCR when the device is first powered up or when a power-on

reset is performed. These defaults are set at the factory after fabrication. After the CSM command that loads

the DCR (96h) is executed, the defaults no longer define the device operation; instead, the new configuration

takes effect. To restore the default state, either perform a power-on reset or load the DCR with the reset-state

settings using the 96h command sequence.

The TMS28F033 has two types of defaults: a fuse-bit-option default and a standard default. The difference

between the two types is that a fuse-bit-option default can be optionally set (0 or 1) at the factory, whereas a

standard default is always set to 0 at the factory. The DCR has eight fuse-bit-option defaults, DCR0 – DCR7,

and eight standard defaults, DCR24 – DCR31. The X-latency bits DCR28 – DCR29 are the only exceptions to

these two types of defaults. These bits default to 00 (standard defaults), except when the device is in x16 mode

as 10 (see Table 8). It is important to note that even though DCR28 – DCR29 functions as 10 for these

exceptions, they are still read (with the DCR read command 90h) as 00, instead of 10.

Table 8. Device Configuration Register Bit Definitions and Functions

DCR BIT

FUNCTION

DATA

COMMENTS

DCR0

Control pin configuration

0 = Basic Control Pin Set

1 = Enhanced Control Pin Set

(see Note 5 and Note 6)

When DCR0 = 0, the device functions with the basic

pin set, and the internal pullups are enabled for the RP,

BAA/LRV, and WORD/DIS pins. When DCR0 = 1, the

device

functions

with

the

enhanced

pin

set.

See the Terminal Functions table and Table 9

DCR1

OE functionality

0 = Synchronous OE

1 = Asynchronous OE

(see Note 5 and Note 6)

When DCR1 = 0, OE functions as a synchronous

output enable. When DCR1 = 1, OE functions

asynchronously. See the Terminal Functions table and

Table 9

DCR2

WE functionality

0 = Synchronous WE

1 = Asynchronous WE

(see Note 5 and Note 6)

When DCR2 = 0, WE functions as a synchronous write

enable.

When

DCR2

=

1,

WE

functions

asynchronously. See the Terminal Functions table and

Table 9

DCR3

WORD/DIS functionality

0 = DIS, and x32 mode

1 = WORD

(see Note 5 and Note 6)

When DCR3 = 0, pin 78 functions as output disable

(DIS) and the device is forced into x32 mode. When

DCR3 = 1, pin 78 functions as WORD (for x16 mode,

set WORD = VIL; and for x32 mode, set WORD = VIH).

See the Terminal Functions table and Table 9

DCR4

BAA/LRV functionality

0 = LRV

1 = BAA

(see Note 5 and Note 6)

When DCR4 = 0, pin 79 functions as low regulator

voltage (LRV) and its status can be monitored in SB4.

When DCR4 = 1, pin 79 functions as burst address

advance (BAA). See the Terminal Functions table and

Table 9

DCR5

Main block control

0 = 3 Main Blocks

1 = 4 Main Blocks

(see Note 5 and Note 6)

When DCR5 = 0, the main memory array has three

blocks, as seen in Figure 1. When DCR5 = 1, the main

memory array has four blocks, as seen in Figure 2.

See Table 1.

DCR7, DCR6

Internal timing control

Refer to switching characteristics

for tCHCH1 and tCHQV

(see Note 5 and Note 6)

These bits are used to optimize device performance

(see switching characteristics table).

NOTES:

5. The default setting for these bits is set at the factory prior to shipping.

6. These bits return to the default setting after a power-on reset is performed; therefore, it is necessary to program these bits to the

desired configuration.