TMS28F033 datasheet(38/52 Pages) TI

38 / 52 page

CLK

A–1–A16

(word-wide)

LBA

BAA

RY/BY

VDDI/VDDE

DQ0–DQ7 and

DQ24–DQ31

(word-wide)

BASIC/ENHANCED

PIN SET

DCR0

MODE

DCR1

MODE

DCR2

DIS/WORD

DCR3

LRV/BAA

DCR4

BURST

LENGTH

DCR25,24

BURST

LATENCY (X)

DCR29,28

BURST

LATENCY (Y)

DCR30

x16 WRITE

OPTION

DCR31

See Note E

—

Enhanced pin set (DCR0 = 1)

(see Note F)

(see Note G)

(see Note H)

(see Note I)

NOTES: A. X is a don’t care.

B. See Table 8 through Table 12 for DCR setting descriptions.

C. Address A3 can be loaded as early as clock 6 for overlapped burst reads.

D. Interleave burst requires LBO = VIH.

E. Interleave burst is available only with the enhanced pin set.

F. Interleave burst is available only with the 16-bit data bus, which requires DCR3 = 1 with WORD = VIL.

G. For synchronous OE (DCR1 = 0), BAA is not required to burst if OE is used to control the burst (DCR[29:28] = 00).

H. Interleave burst is available only with MOD4.

I. Interleave MOD4 burst is available with 3–1–1–1 and 4–1–1–1.

Figure 15. 4–1–1–1 MOD4 Interleave Burst Read With Device Configuration Register Settings

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TMS28F033 Datasheet(PDF) 38 Page - Texas Instruments

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