TMS28F033 datasheet(14/52 Pages) TI

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TMS28F033

4194304-BIT

SYNCHRONOUS FLASH MEMORY

SMJS833 – NOVEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

control pin functions (continued)

Table 9. DCR-Controlled Pin Functions

PIN NUMBER

DCR BIT (x)

DCRx = 0

DCRx = 1

Hi-Z

RY/BY

3.3-V IO

3/5IO

Chip Enabled

Synchronous OE

Asynchronous OE

Synchronous WE

Asynchronous WE

DIS

WORD

LRV

BAA

Linear Burst

LBO

burst length

The burst length, as determined by DCR24 – DCR25, is the length of the data sequence (or number of memory

locations) to be read for each entered address. When using BAA (DCR4 = 1), there are four possibilities for burst

length: modulo 4 addressing (MOD4), MOD8, MOD16, and MOD32. For MOD4, when the initial address is

XXXX0h, the internal burst address order is 0–1–2–3 for linear burst (LBO = VIL). MOD8, MOD16, and MOD32

function as 0–1–2... 6–7, 0–1–2... 14–15, and 0–1–2... 30–31, respectively. Burst delivery is critical word

first with wrap around.

burst access and burst performance

The notation X–Y–...–Y is used to denote the X and Y burst latency for the data sequence to be burst.

X-latency (DCR28 – DCR29) denotes the number of clock cycles required to access the first word/double-word

from memory, and Y-latency (DCR30) denotes the number of clock cycles required to access the subsequent

words/double-words to complete the cache fill (see Table 10). The four X-latency possibilities are:

OE-controlled, and 3, 4, or 5 clock cycles. The two Y-latency possibilities are 1 and 2 clock cycles. The burst

performance for < 25 MHz, < 33 MHz, and < 40 MHz for linear and interleave burst order is listed in Table 11.

Table 10. Burst Access Combinations (see Note 7)

DEVICE CONFIGURATION REGISTER BITS

BURST ACCESS

DCR30

DCR29

DCR28

(CLOCK CYCLES TO READ)

X–1– . . . –1 (see Note 8)

3–1– ...–1

4–1– ...–1

5–1– ...–1

X–2– . . . –2 (see Note 8)

4–2– ...–2

NOTES:

7. These burst access combinations are available for MOD4, MOD8, MOD16, and MOD32.

8. For both DCR30 – DCR28 = 000 and DCR30 – DCR28 = 100, the X-latency is OE-controlled.

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