18

11

12

13

14

15

16

17

6

4

3

5

78

9

12

10

00000h

X

Hi–Z

FFh

PA

1 or 0

00000h

CLK

A0–A16

0 or 1

X

E

WE

WR

X...Xh

Data

Data

40h or 04h

Hi–Z

BAA

LBA

OE

RY/BY

QV

Hi–Z

DQ0–DQ7

and

DQ24–DQ31

(word-wide)

RP

Valid SR

Write

Program-

Setup

Command

Write Valid

Address and Data

Automated Two 16-bit

Word Programming

Read Status

Register Bits

Write

Read-Array

Command

BASIC/ENHANCED

PIN SET

DCR0

OE

MODE

DCR1

WE

MODE

DCR2

DIS/WORD

DCR3

LRV/BAA

DCR4

BURST

LENGTH

DCR25,24

BURST

LATENCY (X)

DCR29,28

BURST

LATENCY (Y)

DCR30

x16 WRITE

OPTION

DCR31

Basic pin set (DCR0 = 0

0

0

1

(see Note D)

X

(see Note E)

XX

XX

X

1

(see Note F)

Enhanced pin set (DCR0 = 1)

0

0

1

(see Note D)

X

(see Note E)

XX

XX

X

1

(see Note F)

NOTES: A. X is a don’t care. PA is the address to be programmed.

B. See Table 8 for DCR setting descriptions.

C. Wait states can be inserted between the address and data phases of a command or write-data cycle. In addition, wait states can be inserted between the data

phase of the current cycle and the address phase of the next cycle (see Figure 22).

D. Three-cycle write is available only with the 16-bit data bus, which requires DCR3 = 1 and WORD=VIL.

E. For LRV usage (DCR4 = 0) see Figure 6, and for DCR4 = 1 see Figure 7.

F. When using the 16-bit data bus (DCR3 = 1 and WORD = VIL), both two-cycle writes (DCR31 = 0) and three-cycle writes (DCR31 = 1) are available. For synchronous

two-cycle write timing, see Figure 22.

Figure 24. Synchronous Write-Cycle Timing (Three-Cycle Write) with Device Configuration Register Settings

ADVANCE INFORMATION