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FXLS93421 Datasheet(PDF) 174 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 174 Page - NXP Semiconductors |
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174 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor time after the initial sync pulse detection, the counter is compared against a limit (the minimum value of tSYNC). If the counter is above the limit, a valid sync pulse is detected. If the Sync pulse is valid, the following occur: 1. The valid Sync pulse detection signal is set. 2. The detection counter is reset and disabled for tSYNC_OFF (referenced from tTRIG). tSYNC_OFF can be programmed by the user via the PDCM_CMD_B_x registers. See Section 11.2.19 for details on the programmable option, and Section 10.12 for timing specifications for each option. 3. The Sync pulse detection low-pass filter is reset for a specified time (tSYNC_LPF_RESET). If the Sync pulse is invalid, all timers are reset, and the detector becomes sensitive within 2 µs. The output of the comparator is monitored at the SampCLK frequency. Once the comparator output goes high, all of the internal timers are started, so that the tTRIG jitter is minimized. Response tA_SYNC_DLY tSYNC_LPF_RST_ST tTRIG tSYNC_LPF_RST tPD_DLY tPD_ON tSYNC_OFF_xxx tTIMESLOTx aaa-030669 sync_pulse_PD sync off sync_LPF_reset VSYNC_COMP sync pulse Figure 84. Synchronization pulse detection timing FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 174 / 254 |
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