FXLS93421 datasheet(176/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

aaa-030672

IR_PSI5

SB1

SB0

`0'

bit value

`0'

data bit

tTRAN = tBIT * (2+DATASIZE+(P_CRC?3:1))

tBIT

tFRAME

`1'

`0'

`1'

`0'

`1'

PAR

SB1

Figure 87. Example Manchester encoded data transfer - PSI5-x10x

13.3.2.1 PSI5-x10P transmission mode

The device can be configured to transmit 10-bit data with parity by setting the

PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG

Start Bits

Sensor data (See Section 11.6.4.9)

Parity

Table 259. PSI5-x10P transmission mode

13.3.2.2 PSI5-x10C transmission mode

The device can be configured to transmit 10-bit data with 3-bit CRC by setting the

PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG

Start bits

Sensor data (See Section 11.6.4.9)

CRC

Table 260. PSI5-x10C transmission mode

13.3.2.3 PSI5-x16P transmission mode

The device can be configured to transmit 16-bit data with parity by setting the

PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG

the data packet and the lower 6-bits are all zeros.

Start bits

Sensor data (See Section 11.6.4.9)

Parity

D9 D10 D11 D12 D13 D14 D15

Init Data

10-bit Initialization Data as specified in Section 13.4.2.1

Table 261. PSI5-x16P transmission mode

13.3.2.4 PSI5-x16C transmission mode

The device can be configured to transmit 16-bit data with 3-bit CRC by setting the

PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG

the data packet and the lower 6-bits are all zeros.

Start bits

Sensor data (See Section 11.6.4.9)

CRC

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C2 C1 C0

Table 262. PSI5-x16C transmission mode

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

176 / 254

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