FXLS93421 datasheet(196/254 Pages) NXP

196 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Start bits

Sensor

address

Function

code

Data

CRC

S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy RA6 RA7 D0 Sy D1 D2 D3 Sy D4 D5 D6 Sy D7 C2 C1 Sy C0

Table 290. Programming mode via PSI5 XLONG command data format with sync bits

Response

RD1

RD0

$1E2

$3FF

Table 291. Programming mode via PSI5 XLONG command data format with sync bits - response

Once a command is received and verified, the device expects 2 to 3 consecutive sync

pulses (depending upon the command message lengths described in Table 292). There

is no delay restriction between the command and the first sync pulse for the response.

Once the first sync pulse for the response is received, each successive response sync

pulse must be received within the programming mode sync pulse period specified (tS-

S_PM) or a framing error may occur.

For each of these sync pulses, The device will respond with the following settings:

Parameter

Value

Time Slot

tTIMESLOT_DC0

Data Size

10-bit data

Error Checking

Even Parity

Baud Rate

125 kBd

Sync Pulse Pulldown

Disabled

Table 292. Programming mode via PSI5 response message settings

13.10.2.3 Short frame command and response format

Short frames are the simplest type of command message. No data is transmitted in a

short frame command. Only specific instructions are performed in response to short

frame commands. The short frame format is shown in Table 293. Short frame commands

and responses are defined in Section 13.10.3.

The device only supports a short command for programming mode entry.

Start bits

Sensor address

Function code

CRC

SA0

SA1

SA2

FC0

FC1

FC2

Table 293. Programming mode via PSI5 short command

Response

RD1

$1E2

$3FF

Table 294. Response format

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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