FXLS93421 datasheet(197/254 Pages) NXP

197 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

13.10.2.4 Long frame command and response format

Long frames allow for the transmission of data nibbles for register writes. The device

can provide register data in response to a read or write request. the long frame format is

shown in Table 295. The device does not support the long frame command.

Start Bits

Sensor Address

Function Code

Data

CRC

S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy D0 D1 D2 Sy D3 C2 C1 Sy C0

Table 295. Programming mode via PSI5 long command

Response

RD1

RD0

$1E2

$3FF

Table 296. Response format

13.10.2.5 Extra long frame command and response format

Extra long frames allow for the transmission of address and data bytes for register reads

and writes. The device can provide register data in response to a read or write request.

The extra long frame format is shown in Table 297. Extra long frame commands and

responses are defined in Section 13.10.3.

The device supports register read and register write extra long commands.

Start Bits

Sensor

Address

Function

Code

Data

CRC

S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy RA6 RA7 D0 Sy D1 D2 D3 Sy D4 D5 D6 Sy D7 C2 C1 Sy C0

Table 297. Programming mode via PSI5 long command

Response

RD1

RD0

$1E2

$3FF

Table 298. Response format

13.10.2.6 Command message CRC

Programming mode command error checking is accomplished by a 3-bit CRC. The 3-

bit CRC is calculated using all message bits except start bits and sync bits. The CRC

verification uses a generator polynomial of g(x) = X3+X+1, with a non-direct seed value

= '111'. The message data is provided to the CRC calculator in the order received (LSB

first, SAdr, FC, RAdr, Data), and then augmented with '000'. Table 263 shows some

example CRC calculation values for 10-bit data transmissions.

The calculated CRC is then compared against the received 3-bit CRC (received MSB

first). If a CRC mismatch is detected, the device responds with a CRC Error response as

defined in Section 13.10.4.

13.10.2.7 Command sync pulse blanking time

In programming mode and programming mode entry, the device employs a fixed sync

pulse blanking time of tSYNC_OFF_250 regardless of the state of the PDCM_CMD_B

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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