FXLS93421 datasheet(199/254 Pages) NXP

199 / 254 page

NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

ErrN

Mnemon

Description

Supported

1100

1101

1110

1111

Table 301. Error response summary...continued

ErrN is transmitted in the 4 LSBs of RD1. All other bits in the response data field are set

to '0'.

13.11 PSI5 OTP programming procedure

1. Enter programming mode.

2. Set VCC = VPP

3. Load desired data into the desired registers using PSI5 Write commands.

4. Write the necessary OTP program sequence to the WRITE_OTP_EN register for the

desired OTP region to be written.

5. Delay tPROG_TIME after the completion of the Write OTP program to allow for

completion of the OTP writes.

6. Read the DEVSTAT and DEVSTAT2 registers to confirm that no errors occurred

during the OTP writes.

7. Read back the register values that were written and compare to the desired values to

confirm successful OTP writes.

Refer to the PSI5 OTP Programming Procedure Application Note for further details on

OTP programming.

14 Standard 32-bit SPI protocol

The device includes a standard SPI protocol requiring 32-bit data packets. The device is

a slave device requires that the base clock value be low (CPOL = 0) with data captured

on the rising edge of the clock and data propagated on the falling edge of the clock

(CPHA = 0). The most significant bit is transferred first (MSB first). SPI transfers are

completed through a sequence of two phases. During the first phase, the command is

transmitted from the SPI master to the device. During the second phase, response data

is transmitted from the slave device. MOSI and SCLK transitions are ignored when SS_B

is not asserted.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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