FXLS93421 datasheet(202/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

Section 14.5.4. The Register Read response includes the register contents at the rising

edge of SS_B for the Register Read command.

14.3.1.1 Register read command message format

MSB

LSB

Command C[3:0]

Fixed Bits:

Must = 0x0

8-bit CRC

RA[7:1]

RA[0] 0

CRC[7:0]

Table 305. Register read command message format

Bit field

Definition

C[3:0]

RA[7:1]

RA[7:1] contains the word address of the register to be read.

CRC[7:0]

CRC. See Section 14.4

Table 306. Register read command message format description

14.3.1.2 Register read response message format

MSB

LSB

Command C[0], [3:1]

Basic

Status

Unused

Data

= 0x0

of RA[7:1] High Byte

of RA[7:1] Low Byte

8-bit CRC

RD[15:8]

RD[7:0]

CRC[7:0]

Table 307. Register read response message format

Bit field

Definition

C[0], [3:1]

ST[1:0]

Status. See Section 14.5.1

RD[15:8]

The contents of the register addressed by RA[7:1] High Byte (RA[0] = 1)

RD[7:0]

The contents of the register addressed by RA[7:1] Low Byte (RA[0] = 0)

CRC[7:0]

CRC. See Section 14.4

Table 308. Register read response message format description

14.3.2 Register write command

The device supports a Register Write command. The Register Write command writes

the value specified in RD[7:0] to the register addressed by RA[7:0]. The response to the

command includes the new contents of RA[7:1] high byte (RA[0] = 1) in the upper byte

and the contents of RA[7:1] low byte (RA[0] = 0) in the lower byte.

The response to a register write command is shown in Section 14.3.2.2. The register

write is executed and a response is transmitted on the next SPI message if and only if all

of the following conditions are met:

• No SPI Error is detected (See Section 14.5.6)

FXLS9xxxx

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Product data sheet

Rev. 6 — 8 February 2021

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