CEC1712 datasheet(122/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 122

 2020-2021 Microchip Technology Inc.

10.10 Runtime Registers

The registers listed in the Runtime Register Summary table are for a single instance of the UART. Host access for each

register listed in this table is defined as an offset in the Host address space to the Block’s Base Address, as defined by

the instance’s Base Address Register.

The EC address for each register is formed by adding the Base Address for each instance of the UART shown in the

Block Overview and Base Address Table in Section 3.0, "Device Inventory" to the offset shown in the “Offset” column.

TABLE 10-9:

UART BAUD RATES USING CLOCK SOURCE 48MHz

Desired Baud Rate

BAUD_CLOCK_SEL

Divisor Used to Generate

16X Clock

125000

136400

150000

166700

187500

214300

250000

300000

375000

500000

750000

1500000

3000000

TABLE 10-10: RUNTIME REGISTER SUMMARY

DLAB

Note 1

Offset

00h

Receive Buffer Register

00h

Transmit Buffer Register

10h

Programmable Baud Rate Generator LSB Register

11h

Programmable Baud Rate Generator MSB Register

01h

Interrupt Enable Register

x02h

FIFO Control Register

x02h

Interrupt Identification Register

x03h

Line Control Register

x04h

Modem Control Register

x05h

Line Status Register

x06h

Modem Status Register

x07h

Scratchpad Register

Note 1: DLAB is bit 7 of the Line Control Register.

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