CEC1712 datasheet(126/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 126

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Transmitter Holding Register Empty

MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Iden-

tification Register (refer to Table 10-12). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indi-

cates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new

interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.

Offset

02h

Bits

Description

Type

Default

Reset

Event

7:6

FIFO_EN

These two bits are set when the FIFO CONTROL Register bit 0

equals 1.

R0h

RESET

5:4

Reserved

RES

3:1

INTID

These bits identify the highest priority interrupt pending as indi-

cated by Table 10-12, "Interrupt Control Table". In non-FIFO mode,

Bit[3] is a logic “0”. In FIFO mode Bit[3] is set along with Bit[2] when

a timeout interrupt is pending.

R0h

RESET

IPEND

This bit can be used in either a hardwired prioritized or polled envi-

ronment to indicate whether an interrupt is pending. When bit 0 is a

logic ‘0’ an interrupt is pending and the contents of the IIR may be

used as a pointer to the appropriate internal service routine. When

bit 0 is a logic ‘1’ no interrupt is pending.

R1h

RESET

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