CEC1712 datasheet(130/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 130

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10.10.9

MODEM CONTROL REGISTER

Offset

04h

Bits

Description

Type

Default

Reset

Event

7:5

Reserved

RES

LOOPBACK

This bit provides the loopback feature for diagnostic testing of the

Serial Port. When bit 4 is set to logic “1”, the following occur:

The TXD is set to the Marking State (logic “1”).

The receiver Serial Input (RXD) is disconnected.

The output of the Transmitter Shift Register is “looped back”

into the Receiver Shift Register input.

All MODEM Control inputs (CTS#, DSR#, RI# and DCD#)

are disconnected.

The four MODEM Control outputs (DTR#, RTS#, OUT1 and

OUT2) are internally connected to the four MODEM Control

inputs (DSR#, CTS#, RI#, DCD#).

The Modem Control output pins are forced inactive high.

Data that is transmitted is immediately received.

This feature allows the processor to verify the transmit and receive

data paths of the Serial Port. In the diagnostic mode, the receiver

and the transmitter interrupts are fully operational. The MODEM

Control Interrupts are also operational but the interrupts' sources

are now the lower four bits of the MODEM Control Register instead

of the MODEM Control inputs. The interrupts are still controlled by

the Interrupt Enable Register.

R/W

RESET

3OUT2

Output 2 (OUT2). This bit is used to enable an UART interrupt.

When OUT2 is a logic “0”, the serial port interrupt output is forced

to a high impedance state - disabled. When OUT2 is a logic “1”, the

serial port interrupt outputs are enabled.

R/W

RESET

2OUT1

This bit controls the Output 1 (OUT1) bit. This bit does not have an

output pin and can only be read or written by the CPU.

R/W

RESET

1RTS

This bit controls the Request To Send (RTS#) output.

When bit 1 is set to a logic “1”, the RTS# output is forced to a logic

“0”. When bit 1 is set to a logic “0”, the RTS# output is forced to a

logic “1”.

R/W

RESET

0DTR

This bit controls the Data Terminal Ready (DTR#) output. When bit

0 is set to a logic “1”, the DTR# output is forced to a logic “0”. When

bit 0 is a logic “0”, the DTR# output is forced to a logic “1”.

R/W

RESET

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