CEC1712 datasheet(133/338 Pages) MICROCHIP

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DS00003416C-page 133

CEC1712

10.10.11 MODEM STATUS REGISTER

Offset

06h

Bits

Description

Type

Default

Reset

Event

DCD

This bit is the complement of the Data Carrier Detect (DCD#) input.

If bit 4 of the MCR is set to logic ‘1’, this bit is equivalent to OUT2 in

the MCR.

R0h

RESET

6RI

This bit is the complement of the Ring Indicator (RI#) input. If bit 4

of the MCR is set to logic ‘1’, this bit is equivalent to OUT1 in the

MCR.

R0h

RESET

5DSR

This bit is the complement of the Data Set Ready (DSR#) input. If

bit 4 of the MCR is set to logic ‘1’, this bit is equivalent to DTR# in

the MCR.

R0h

RESET

4CTS

This bit is the complement of the Clear To Send (CTS#) input. If bit

4 of the MCR is set to logic ‘1’, this bit is equivalent to RTS# in the

MCR.

R0h

RESET

DDCD

Delta Data Carrier Detect (DDCD). Bit 3 indicates that the DCD#

input to the chip has changed state.

NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic ‘1’, a MODEM

Status Interrupt is generated.

R0h

RESET

2TERI

Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the RI#

input has changed from logic ‘0’ to logic ‘1’.

R0h

RESET

DDSR

Delta Data Set Ready (DDSR). Bit 1 indicates that the DSR# input

has changed state since the last time the MSR was read.

R0h

RESET

DCTS

Delta Clear To Send (DCTS). Bit 0 indicates that the CTS# input to

the chip has changed state since the last time the MSR was read.

R0h

RESET

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