CEC1712 datasheet(137/338 Pages) MICROCHIP

137 / 338 page

 2020-2021 Microchip Technology Inc.

DS00003416C-page 137

CEC1712

11.3

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

11.3.1

POWER DOMAINS

11.3.2

CLOCK INPUTS

11.3.3

RESETS

11.4

Interrupts

This section defines the Interrupt Sources generated from this block.

11.5

Description

The GPIO Interface refers to all the GPIOxxx pins implemented in the design. GPIO stands for General Purpose I/O.

The GPIO signals may be used by firmware to both monitor and control a pin in “bit-banged” mode. The GPIOs may be

individually controlled via their Pin Control Register or group controlled via the Output and Input GPIO registers. The

GPIO Output Control Select

The GPIO Pin control registers are used to select the alternate functions on GPIO pins (unless otherwise specified), to

control the buffer direction, strength, and polarity, to control the internal pull-ups and pull-downs, for VCC emulation, and

for selecting the event type that causes a GPIO interrupt.

The GPIO input is always live, even when an alternate function is selected. Firmware may read the GPIO input anytime

to see the value on the pin. In addition, the GPIO interrupt is always functional, and may be used for either the GPIO

itself or to support the alternate functions on the pin. See FIGURE 11-1: GPIO Interface Block Diagram on page 136.

Name

Description

VTR_CORE

The registers and logic in this block are powered by VTR_CORE.

Name

Description

48MHz

The 48MHz is used for synchronizing the GPIO inputs.

Name

Description

RESET_SYS

This reset is asserted when VTR_CORE is applied.

RESET_VCC

This is an alternate reset condition, typically asserted when the main

power rail is asserted.

Source

Description

GPIO_Event

Each pin in the GPIO Interface has the ability to generate an interrupt

event. This event may be used as a wake event.

The GPIO Interface can generate an interrupt source event on a high

level, low level, rising edge and falling edge, as configured by the

Interrupt Detection (int_det) bits in the Pin Control Register associated

with the GPIO signal function.

Note:

The minimum pulse width required to generate an inter-

rupt/wakeup event is 5ns.

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