CEC1712 datasheet(141/338 Pages) MICROCHIP

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DS00003416C-page 141

CEC1712

11.6.1

PIN CONTROL REGISTERS

Two Pin Control Registers are implemented for each GPIO. The Pin Control Register format is described in Section

11.6.1.1, "Pin Control Register," on page 141. The Pin Control Register 2 format is described in Section 11.6.1.2, "Pin

Control Register 2," on page 144. Pin Control Register address offsets and defaults for each product are defined in

Section 11.5.3.1, "Pin Control Register Defaults," on page 138.

11.6.1.1

Pin Control Register

Offset

See Table 11-2, "Register Summary"

Bits

Description

Type

Default

Reset

Event

31:25 RESERVED

RES

24 GPIO input from pad

On reads, Bit [24] reflects the state of GPIO input from the pad

regardless of setting of Bit [10].

Note:

This bit is forced high when the selected power well is off

as selected by the Power Gating Signal bits. See

bits[3:2].

Note 11-1 RESET_S

23:17 RESERVED

RES

16 GPIO output data

If enabled by the GPIO Output Control Select bit, the GPIO output

data bit determines the level on the GPIO pin when the pin is config-

ured for the GPIO output function.

On writes:

If enabled via the GPIO Output Control Select

0: GPIO[x] out = ‘0’

1: GPIO[x] out = ‘1’

Note:

If disabled via the GPIO Output Control Select then the

GPIO[x] out pin is unaffected by writing this bit.

On reads:

Bit [16] returns the last programmed value, not the value on the pin.

R/W

(GPIO

Output

Control

Select =

(GPIO

Output

Control

Select=1)

Note 11-1 RESET_S

15 GPIO input disable

This bit can be used to support undervoltage functionality.

1=disable input

0=do not disable input

R/W

Note 11-1 RESET_S

14 RESERVED

RES

13:12 Mux Control

The Mux Control field determines the active signal function for a pin.

00 = GPIO Function Selected

01 = Signal Function 1 Selected

10 = Signal Function 2 Selected

11 = Signal Function 3 Selected

R/W

Note 11-1 RESET_S

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