CEC1712 datasheet(142/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 142

 2020-2021 Microchip Technology Inc.

11 Polarity

0 = Non-inverted

1 = Inverted

When the Polarity bit is set to ‘1’ and the Mux Control bits are greater

than ‘00,’ the selected signal function outputs are inverted and Inter-

rupt Detection (int_det) sense defined in Table 11-3, "Edge Enable

and Interrupt Detection Bits Definition" is inverted. When the Mux

Control field selects the GPIO signal function (Mux = ‘00’), the Polar-

ity bit does not effect the output. Regardless of the state of the Mux

Control field and the Polarity bit, the state of the pin is always

reported without inversion in the GPIO input register.

R/W

Note 11-1 RESET_S

10 GPIO Output Control Select

Every GPIO has two mechanisms to set a GPIO data output: Output

GPIO Bit located in the grouped GPIO Output Registers and the sin-

gle GPIO output data bit located in bit 16 of this register.

This control bit determines the source of the GPIO output.

0 = Pin Control Bit[16] GPIO output data bit enabled

When this bit is zero the single GPIO output data bit is enabled.

(GPIO output data is R/W capable and the Grouped Output GPIO is

disabled (i.e., Read-Only).

1 = Grouped Output GPIO enable

When this bit is one the GPIO output data write is disabled (i.e.,

Read-Only) and the Grouped Output GPIO is enabled (i.e., R/W).

Note:

See description in Section 11.5.1, "Accessing GPIOs".

R/W

Note 11-1 RESET_S

9 GPIO Direction

0 = Input

1 = Output

The GPIO Direction bit controls the buffer direction only when the

Mux Control field is ‘00’ selecting the pin signal function to be

GPIO. When the Mux Control field is greater than ‘00’ (i.e., a non-

GPIO signal function is selected) the GPIO Direction bit has no

affect and the selected signal function logic directly controls the pin

direction.

R/W

Note 11-1 RESET_S

8 Output Buffer Type

0 = Push-Pull

1 = Open Drain

Note:

Unless explicitly stated otherwise, pins with (I/O/OD) or

(O/OD) in their buffer type column in the tables in are

compliant with the following Programmable OD/PP Multi-

plexing Design Rule: Each compliant pin has a program-

mable open drain/push-pull buffer controlled by the

Output Buffer Type bit in the associated Pin Control

interface buffer for all selected functions, including the

GPIO function.

R/W

Note 11-1 RESET_S

Offset

See Table 11-2, "Register Summary"

Bits

Description

Type

Default

Reset

Event

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