CEC1712 datasheet(138/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 138

 2020-2021 Microchip Technology Inc.

11.5.1

ACCESSING GPIOS

There are two ways to access GPIO output data. Bit [10] is used to determine which GPIO output data bit affects the

GPIO output pin.

• Grouped Output GPIO Data

- Outputs to individual GPIO ports are grouped into 32-bit GPIO Output Registers.

• Individual GPIO output data

- Alternatively, each GPIO output port is individually accessible via Bit [16] in the port’s Pin Control Register. On

reads, Bit [16] returns the programmed value, not the value on the pin.

There are two ways to access GPIO input data.

• Input GPIO Data

- Inputs from individual GPIO ports are grouped into 32-bit GPIO Input Registers and always reflect the current

state of the GPIO input from the pad.

• GPIO input from pad

- Alternatively, each GPIO input port is individually accessible via Bit [24] in the port’s Pin Control Register. Bit

[24] always reflects the current state of GPIO input from the pad.

11.5.2

GPIO INDEXING

Each GPIO signal function name consists of a 4-character prefix (“GPIO”) followed by a 3-digit octal-encoded index

number. In the CEC1712 GPIO indexing is done sequentially starting from ‘GPIO000.’

11.5.3

PIN CONTROL REGISTERS

Each GPIO has two Pin Control registers. The Pin Control Register, which is the primary register, is used to read the

value of the input data and set the output either high or low. It is used to select the alternate function via the Mux Control

bits, set the Polarity of the input, configure and enable the output buffer, configure the GPIO interrupt event source,

enable internal pull-up/pull-down resistors, and to enable VCC Emulation via the Power Gating Signals (PGS) control

bits. The Pin Control Register 2 is used to configure the output buffer drive strength and slew rate.

The following tables define the default settings for the two Pin Control registers for each GPIO in each product group.

11.5.3.1

Pin Control Register Defaults

Please refer to Section 3.5, "GPIO Register Assignments" for the Pin Control Register default information.

11.6

GPIO Registers

The registers listed in the Register Summary table are for a single instance of the CEC1712. The addresses of each

Address Table.

Note 11-1

The Base Address indicates where the first register can be accessed in a particular address space

for a block instance.

Note 11-2

The GPIO registers may be accessed by the eSPI Host via the EMI block via GPIO commands or

by direct access if enabled by firmware. See the firmware documentation for a description of this

access method.

TABLE 11-1:

Instance Name

Instance

Number

Host

Address Space

Base Address

GPIO

32-bit internal

address space

4008_1000h

Note 11-1

Note:

Registers and bits associated with GPIOs not implemented are Reserved. Please refer to Section 2.3, "Pin

List" for GPIOs implemented in the chip.

CEC1712 Datasheet(PDF) 138 Page - Microchip Technology

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