CEC1712 datasheet(124/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 124

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10.10.4

PROGRAMMABLE BAUD RATE GENERATOR MSB REGISTER

10.10.5

INTERRUPT ENABLE REGISTER

The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible

to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits

of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identi-

fication Register and disables any Serial Port interrupt out of the CEC1712. All other system functions operate in their

normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register

are described below.

Offset

01h (DLAB=1)

Bits

Description

Type

Default

Reset

Event

BAUD_CLK_SEL

If CLK_SRC is ‘0’:

• 0=The baud clock is derived from the 1.8432MHz.

• 1=IThe baud clock is derived from the 48MHz.

If CLK_SRC is ‘1’:

• This bit has no effect

R/W

RESET

6:0

BAUD_RATE_DIVISOR_MSB

See Section 10.9.1, "Programmable Baud Rate".

R/W

RESET

Offset

01h (DLAB=0)

Bits

Description

Type

Default

Reset

Event

7:4

Reserved

RES

3EMSI

This bit enables the MODEM Status Interrupt when set to logic “1”.

This is caused when one of the Modem Status Register bits

changes state.

R/W

RESET

2ELSI

This bit enables the Received Line Status Interrupt when set to

logic “1”. The error sources causing the interrupt are Overrun, Par-

ity, Framing and Break. The Line Status Register must be read to

determine the source.

R/W

RESET

1ETHREI

This bit enables the Transmitter Holding Register Empty Interrupt

when set to logic “1”.

R/W

RESET

ERDAI

This bit enables the Received Data Available Interrupt (and timeout

interrupts in the FIFO mode) when set to logic “1”.

R/W

RESET

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