CD1865 datasheet(69/150 Pages) INTEL

69 / 150 page

Intelligent Eight-Channel Communications Controller — CD1865

Datasheet

For details on transmitter flow-control operation, refer to the Section 7.3 on page 72.

7.2.2

FIFO Operation

An 8-byte FIFO is provided for each transmit channel. In addition to the 8-byte FIFO, the CD1865

also contains a Transmit Holding register and the Transmit Shift register for each channel.

However, when servicing a Transmit Service Request, only up to eight characters can be written

into the Transmit Data register (TDR) consecutively.

7.2.3

Transmit Service Requests

Generating a Transmit Service Request depends on control bits in the Enable register (). Setting the

TxRdy bit of the specifies that a Transmit Service Request be generated when the FIFO is empty.

When this condition occurs, there is still one character in the Transmit Holding register and another

character in the Transmit Shift register. The host CPU, therefore, has up to two-character times to

respond before the transmitter output goes into the idle (Mark) condition.

Setting the TxMpty bit instead of the TxRdy bit of the specifies that a Transmit Service Request be

generated only when the FIFO, the Transmit Holding register, and the Transmit Shift register are

empty. When this condition occurs, it means that all characters are completely transmitted and the

channel can now be re-configured. It is recommended that one of the two bits be set as needed, but

do not set both bits at the same time.

End of a service request must be signalled to the CD1865 by writing to the End Of register ().

Figure 24. Transmitter Operation

FULL /

EMPTY

BIT

TRANSMITTER HOLDING REGISTER

TRANMSITTER SHIFT REGISTER

TRANSMITTER

FIFO

BACKGROUND CODE:

FIFO-TO-H.R. TRANSFER, FLOW

CONTROL, OTHER FEATURES

FOREGROUND CODE:

BIT DISASSEMBLY,

H.R.-TO-S.R. TRANSFER

(POLLING LOOP)

(INTERRUPT-DRIVEN)

RTS

OUT

CTS

CD1865 Datasheet(PDF) 69 Page - Intel Corporation