CD1865 datasheet(36/150 Pages) INTEL

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CD1865 — Intelligent Eight-Channel Communications Controller

Datasheet

1. Provide three levels of interrupt support, with three separate levels and three separate vectors.

This is well-suited to Motorola 680X0 processors.

2. Provide a single level of interrupt support; this is an effective method when using 8-bit

processors such as the Z-80 and many Intel

microprocessors.

3. Poll the device directly in software.

Once the host has ‘noticed’ the service request, it has the following two choices for acknowledging

the request and beginning to service it:

• Acknowledge the request by a hardware-based service acknowledgment, as is typically done

in interrupt-driven systems.

• Acknowledge the request in software by reading from a register in the CD1865.

Thus, there are six theoretically possible options for interfacing the CD1865 to the host system.

Two of the methods (2a and 3a) are not practical to implement without external hardware, and offer

no performance advantage. Each of the other four methods has advantages and drawbacks

depending on the type of host CPU being used and whether or not that host CPU supports more

than one CD1865. The four methods used are listed in Table 4.

• This method is called ‘Full Interrupt – Type A’. The system is fully interrupt driven with

acknowledgments in hardware. It requires a host with at least three interrupt priority levels

available and the ability to acknowledge on multiple levels. This is the technique used by

Motorola 680X0 processors. It is the most efficient method when the host CPU has a relatively

fast interrupt context switch time and when the host CPU has duties other than driving the

CD1865s.

• This method is called ‘Full Interrupt – Type B’. It still has three levels of interrupt, but

provides a single acknowledgment level. It is commonly used in Intel-type processor systems

where there is an 8259A interrupt controller. The 8259A receives the three levels of interrupt,

but it provides its own vector to the host rather than that of the CD1865s. Then the host

acknowledges the CD1865s Service Request by reading the Vector register.

• This method is called ‘Single Interrupt’, and is best-suited to systems having only a single

interrupt input, such as most 8-bit microprocessors. After the host receives its interrupt and is

entering its interrupt service routine, it reads the CD1865 to evaluate which of the three types

of service requests is responsible for the interrupt.Then it acknowledges the interrupt by

reading the appropriate Request Acknowledge register. Note that the single interrupt signal

must be generated by the logical OR of the three request outputs with external output gates,

not by ‘wire-OR’ing’ them.

Table 4.

Service Request Methods

How the host detects the Service Request

1. Three-level

Hardware

Interrupt

2. Single-level

Hardware

Interrupt

3. Software

Polling

How the host

acknowledges the

Interrupt

a. Hardware-based

service

acknowledge

Full Interrupt – Type A

2a Not recommended

(Inefficient)

3a Not recommended

(Inefficient)

b. Software-based

service

acknowledge

Full Interrupt – Type B

Single Interrupt

Software Polled

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